122b0220fd
The data layout strings do not have any effect on llc tests and will become misleadingly out of date as we continue to update the canonical data layout, so remove them from the tests. Differential Revision: https://reviews.llvm.org/D105842
247 lines
9.1 KiB
LLVM
247 lines
9.1 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s
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; Currently all wasm atomic memory access instructions are sequentially
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; consistent, so even if LLVM IR specifies weaker orderings than that, we
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; should upgrade them to sequential ordering and treat them in the same way.
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target triple = "wasm32-unknown-unknown"
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;===----------------------------------------------------------------------------
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; Atomic loads
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;===----------------------------------------------------------------------------
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; The 'release' and 'acq_rel' orderings are not valid on load instructions.
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; CHECK-LABEL: load_i32_unordered:
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; CHECK: i32.atomic.load $push0=, 0($0){{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @load_i32_unordered(i32 *%p) {
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%v = load atomic i32, i32* %p unordered, align 4
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ret i32 %v
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}
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; CHECK-LABEL: load_i32_monotonic:
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; CHECK: i32.atomic.load $push0=, 0($0){{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @load_i32_monotonic(i32 *%p) {
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%v = load atomic i32, i32* %p monotonic, align 4
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ret i32 %v
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}
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; CHECK-LABEL: load_i32_acquire:
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; CHECK: i32.atomic.load $push0=, 0($0){{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @load_i32_acquire(i32 *%p) {
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%v = load atomic i32, i32* %p acquire, align 4
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ret i32 %v
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}
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; CHECK-LABEL: load_i32_seq_cst:
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; CHECK: i32.atomic.load $push0=, 0($0){{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @load_i32_seq_cst(i32 *%p) {
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%v = load atomic i32, i32* %p seq_cst, align 4
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ret i32 %v
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}
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;===----------------------------------------------------------------------------
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; Atomic stores
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;===----------------------------------------------------------------------------
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; The 'acquire' and 'acq_rel' orderings aren’t valid on store instructions.
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; CHECK-LABEL: store_i32_unordered:
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; CHECK-NEXT: .functype store_i32_unordered (i32, i32) -> (){{$}}
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; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
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; CHECK-NEXT: return{{$}}
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define void @store_i32_unordered(i32 *%p, i32 %v) {
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store atomic i32 %v, i32* %p unordered, align 4
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ret void
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}
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; CHECK-LABEL: store_i32_monotonic:
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; CHECK-NEXT: .functype store_i32_monotonic (i32, i32) -> (){{$}}
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; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
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; CHECK-NEXT: return{{$}}
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define void @store_i32_monotonic(i32 *%p, i32 %v) {
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store atomic i32 %v, i32* %p monotonic, align 4
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ret void
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}
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; CHECK-LABEL: store_i32_release:
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; CHECK-NEXT: .functype store_i32_release (i32, i32) -> (){{$}}
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; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
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; CHECK-NEXT: return{{$}}
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define void @store_i32_release(i32 *%p, i32 %v) {
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store atomic i32 %v, i32* %p release, align 4
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ret void
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}
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; CHECK-LABEL: store_i32_seq_cst:
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; CHECK-NEXT: .functype store_i32_seq_cst (i32, i32) -> (){{$}}
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; CHECK-NEXT: i32.atomic.store 0($0), $1{{$}}
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; CHECK-NEXT: return{{$}}
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define void @store_i32_seq_cst(i32 *%p, i32 %v) {
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store atomic i32 %v, i32* %p seq_cst, align 4
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ret void
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}
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;===----------------------------------------------------------------------------
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; Atomic read-modify-writes
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;===----------------------------------------------------------------------------
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; Out of several binary RMW instructions, here we test 'add' as an example.
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; The 'unordered' ordering is not valid on atomicrmw instructions.
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; CHECK-LABEL: add_i32_monotonic:
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; CHECK-NEXT: .functype add_i32_monotonic (i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @add_i32_monotonic(i32* %p, i32 %v) {
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%old = atomicrmw add i32* %p, i32 %v monotonic
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ret i32 %old
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}
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; CHECK-LABEL: add_i32_acquire:
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; CHECK-NEXT: .functype add_i32_acquire (i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @add_i32_acquire(i32* %p, i32 %v) {
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%old = atomicrmw add i32* %p, i32 %v acquire
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ret i32 %old
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}
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; CHECK-LABEL: add_i32_release:
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; CHECK-NEXT: .functype add_i32_release (i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @add_i32_release(i32* %p, i32 %v) {
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%old = atomicrmw add i32* %p, i32 %v release
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ret i32 %old
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}
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; CHECK-LABEL: add_i32_acq_rel:
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; CHECK-NEXT: .functype add_i32_acq_rel (i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @add_i32_acq_rel(i32* %p, i32 %v) {
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%old = atomicrmw add i32* %p, i32 %v acq_rel
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ret i32 %old
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}
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; CHECK-LABEL: add_i32_seq_cst:
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; CHECK-NEXT: .functype add_i32_seq_cst (i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.add $push0=, 0($0), $1{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @add_i32_seq_cst(i32* %p, i32 %v) {
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%old = atomicrmw add i32* %p, i32 %v seq_cst
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ret i32 %old
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}
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; Ternary RMW instruction: cmpxchg
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; The success and failure ordering arguments specify how this cmpxchg
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; synchronizes with other atomic operations. Both ordering parameters must be at
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; least monotonic, the ordering constraint on failure must be no stronger than
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; that on success, and the failure ordering cannot be either release or acq_rel.
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; CHECK-LABEL: cmpxchg_i32_monotonic_monotonic:
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; CHECK-NEXT: .functype cmpxchg_i32_monotonic_monotonic (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_monotonic_monotonic(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new monotonic monotonic
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_acquire_monotonic:
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; CHECK-NEXT: .functype cmpxchg_i32_acquire_monotonic (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_acquire_monotonic(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new acquire monotonic
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_release_monotonic:
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; CHECK-NEXT: .functype cmpxchg_i32_release_monotonic (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_release_monotonic(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new release monotonic
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_acq_rel_monotonic:
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; CHECK-NEXT: .functype cmpxchg_i32_acq_rel_monotonic (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_acq_rel_monotonic(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new acq_rel monotonic
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_seq_cst_monotonic:
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; CHECK-NEXT: .functype cmpxchg_i32_seq_cst_monotonic (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_seq_cst_monotonic(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst monotonic
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_acquire_acquire:
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; CHECK-NEXT: .functype cmpxchg_i32_acquire_acquire (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_acquire_acquire(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new acquire acquire
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_release_acquire:
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; CHECK-NEXT: .functype cmpxchg_i32_release_acquire (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_release_acquire(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new release acquire
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_acq_rel_acquire:
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; CHECK-NEXT: .functype cmpxchg_i32_acq_rel_acquire (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_acq_rel_acquire(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new acq_rel acquire
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_seq_cst_acquire:
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; CHECK-NEXT: .functype cmpxchg_i32_seq_cst_acquire (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_seq_cst_acquire(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst acquire
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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; CHECK-LABEL: cmpxchg_i32_seq_cst_seq_cst:
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; CHECK-NEXT: .functype cmpxchg_i32_seq_cst_seq_cst (i32, i32, i32) -> (i32){{$}}
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; CHECK: i32.atomic.rmw.cmpxchg $push0=, 0($0), $1, $2{{$}}
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; CHECK-NEXT: return $pop0{{$}}
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define i32 @cmpxchg_i32_seq_cst_seq_cst(i32* %p, i32 %exp, i32 %new) {
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%pair = cmpxchg i32* %p, i32 %exp, i32 %new seq_cst seq_cst
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%old = extractvalue { i32, i1 } %pair, 0
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ret i32 %old
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}
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