16086d47c0
If the icmp is in a different block, then the register for the icmp
operand may not be initialized, as it nominally does not have
cross-block uses. Add a check that the icmp is in the same block
as the branch, which should be the common case.
This matches what X86 FastISel does:
5b6b090cf2/llvm/lib/Target/X86/X86FastISel.cpp (L1648)
The "not" transform that could have a similar issue is dropped
entirely, because it is currently dead: The incoming value is
a branch or select condition of type i1, but this code requires
an i32 to trigger.
Fixes https://bugs.llvm.org/show_bug.cgi?id=51651.
Differential Revision: https://reviews.llvm.org/D108840
40 lines
1.1 KiB
LLVM
40 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=wasm32-unknown-unknown -wasm-disable-explicit-locals -wasm-keep-registers < %s | FileCheck %s
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define i32 @test(i8* %p, i8* %p2) {
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; CHECK-LABEL: test:
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; CHECK: .functype test (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.load8_u $3=, 0($0)
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; CHECK-NEXT: i32.eqz $2=, $3
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; CHECK-NEXT: i32.store8 0($1), $3
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; CHECK-NEXT: # %bb.1: # %bb2
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; CHECK-NEXT: i32.const $4=, 1
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; CHECK-NEXT: i32.and $5=, $2, $4
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; CHECK-NEXT: block
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; CHECK-NEXT: br_if 0, $5 # 0: down to label0
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; CHECK-NEXT: # %bb.2: # %bb4
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; CHECK-NEXT: i32.const $6=, 0
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; CHECK-NEXT: return $6
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; CHECK-NEXT: .LBB0_3: # %bb3
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; CHECK-NEXT: end_block # label0:
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; CHECK-NEXT: i32.const $7=, 1
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; CHECK-NEXT: return $7
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%v = load i8, i8* %p
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%v.ext = zext i8 %v to i32
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%cond = icmp eq i32 %v.ext, 0
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; Cause FastISel abort.
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%shl = shl i8 %v, 0
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store i8 %shl, i8* %p2
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br label %bb2
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bb2:
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br i1 %cond, label %bb3, label %bb4
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bb4:
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ret i32 0
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bb3:
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ret i32 1
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}
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