5f7cdb2eff
We need to produce a setcc instruction which has an 8-bit result. This gets rid of a bunch of cases that were using the s1->s8/s16/s32/s64 handling in selectZExt. I'm not very familiar with GlobalISel yet so I'm not yet sure the best way to do things. I'd especially like feedback on the best way to handle the currently split 32-bit and 64-bit mode handling. Differential Revision: https://reviews.llvm.org/D85814
481 lines
15 KiB
YAML
481 lines
15 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define i8 @test_i8(i32 %a, i8 %f, i8 %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i8 [ %f, %cond.true ], [ %t, %cond.false ]
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ret i8 %cond
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}
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define i16 @test_i16(i32 %a, i16 %f, i16 %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i16 [ %f, %cond.true ], [ %t, %cond.false ]
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ret i16 %cond
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}
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define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]
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ret i32 %cond
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}
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define i64 @test_i64(i32 %a, i64 %f, i64 %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ]
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ret i64 %cond
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}
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define float @test_float(i32 %a, float %f, float %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
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ret float %cond
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}
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define double @test_double(i32 %a, double %f, double %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi double [ %f, %cond.true ], [ %t, %cond.false ]
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ret double %cond
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}
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...
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---
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name: test_i8
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 3, class: gpr, preferred-register: '' }
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- { id: 4, class: gpr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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- { id: 7, class: gpr, preferred-register: '' }
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body: |
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; ALL-LABEL: name: test_i8
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; ALL: bb.0.entry:
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; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; ALL: liveins: $edi, $edx, $esi
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
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; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
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; ALL: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
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; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
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; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
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; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
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; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
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; ALL: JCC_1 %bb.2, 5, implicit $eflags
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; ALL: bb.1.cond.false:
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; ALL: successors: %bb.2(0x80000000)
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; ALL: bb.2.cond.end:
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; ALL: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
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; ALL: $al = COPY [[PHI]]
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; ALL: RET 0, implicit $al
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bb.1.entry:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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liveins: $edi, $edx, $esi
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%0:gpr(s32) = COPY $edi
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%3:gpr(s32) = COPY $esi
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%1:gpr(s8) = G_TRUNC %3(s32)
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%4:gpr(s32) = COPY $edx
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%2:gpr(s8) = G_TRUNC %4(s32)
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%5:gpr(s32) = G_CONSTANT i32 0
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%8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
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%6:gpr(s1) = G_TRUNC %8(s8)
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G_BRCOND %6(s1), %bb.3
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bb.2.cond.false:
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successors: %bb.3(0x80000000)
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bb.3.cond.end:
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%7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1
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$al = COPY %7(s8)
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RET 0, implicit $al
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...
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---
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name: test_i16
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 3, class: gpr, preferred-register: '' }
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- { id: 4, class: gpr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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- { id: 7, class: gpr, preferred-register: '' }
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body: |
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; ALL-LABEL: name: test_i16
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; ALL: bb.0.entry:
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; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; ALL: liveins: $edi, $edx, $esi
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
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; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
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; ALL: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
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; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
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; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
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; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
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; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
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; ALL: JCC_1 %bb.2, 5, implicit $eflags
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; ALL: bb.1.cond.false:
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; ALL: successors: %bb.2(0x80000000)
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; ALL: bb.2.cond.end:
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; ALL: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
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; ALL: $ax = COPY [[PHI]]
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; ALL: RET 0, implicit $ax
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bb.1.entry:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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liveins: $edi, $edx, $esi
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%0:gpr(s32) = COPY $edi
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%3:gpr(s32) = COPY $esi
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%1:gpr(s16) = G_TRUNC %3(s32)
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%4:gpr(s32) = COPY $edx
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%2:gpr(s16) = G_TRUNC %4(s32)
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%5:gpr(s32) = G_CONSTANT i32 0
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%8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
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%6:gpr(s1) = G_TRUNC %8(s8)
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G_BRCOND %6(s1), %bb.3
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bb.2.cond.false:
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successors: %bb.3(0x80000000)
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bb.3.cond.end:
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%7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1
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$ax = COPY %7(s16)
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RET 0, implicit $ax
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...
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---
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name: test_i32
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 3, class: gpr, preferred-register: '' }
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- { id: 4, class: gpr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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body: |
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; ALL-LABEL: name: test_i32
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; ALL: bb.0.entry:
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; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; ALL: liveins: $edi, $edx, $esi
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; ALL: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
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; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
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; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
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; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
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; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
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; ALL: JCC_1 %bb.1, 5, implicit $eflags
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; ALL: JMP_1 %bb.2
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; ALL: bb.1.cond.true:
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; ALL: successors: %bb.3(0x80000000)
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; ALL: JMP_1 %bb.3
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; ALL: bb.2.cond.false:
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; ALL: successors: %bb.3(0x80000000)
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; ALL: bb.3.cond.end:
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; ALL: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; ALL: $eax = COPY [[PHI]]
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; ALL: RET 0, implicit $eax
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bb.1.entry:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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liveins: $edi, $edx, $esi
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s32) = COPY $edx
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%3(s32) = G_CONSTANT i32 0
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%6(s8) = G_ICMP intpred(sgt), %0(s32), %3
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%4:gpr(s1) = G_TRUNC %6(s8)
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G_BRCOND %4(s1), %bb.2
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G_BR %bb.3
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bb.2.cond.true:
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successors: %bb.4(0x80000000)
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G_BR %bb.4
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bb.3.cond.false:
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successors: %bb.4(0x80000000)
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bb.4.cond.end:
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%5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
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$eax = COPY %5(s32)
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RET 0, implicit $eax
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...
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---
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name: test_i64
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 3, class: gpr, preferred-register: '' }
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- { id: 4, class: gpr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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body: |
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; ALL-LABEL: name: test_i64
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; ALL: bb.0.entry:
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; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; ALL: liveins: $edi, $rdx, $rsi
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
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; ALL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
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; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
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; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
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; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
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; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
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; ALL: JCC_1 %bb.1, 5, implicit $eflags
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; ALL: JMP_1 %bb.2
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; ALL: bb.1.cond.true:
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; ALL: successors: %bb.3(0x80000000)
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; ALL: JMP_1 %bb.3
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; ALL: bb.2.cond.false:
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; ALL: successors: %bb.3(0x80000000)
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; ALL: bb.3.cond.end:
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; ALL: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; ALL: $rax = COPY [[PHI]]
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; ALL: RET 0, implicit $rax
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bb.1.entry:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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liveins: $edi, $rdx, $rsi
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%0(s32) = COPY $edi
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%1(s64) = COPY $rsi
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%2(s64) = COPY $rdx
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%3(s32) = G_CONSTANT i32 0
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%6(s8) = G_ICMP intpred(sgt), %0(s32), %3
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%4:gpr(s1) = G_TRUNC %6(s8)
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G_BRCOND %4(s1), %bb.2
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G_BR %bb.3
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bb.2.cond.true:
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successors: %bb.4(0x80000000)
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G_BR %bb.4
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bb.3.cond.false:
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successors: %bb.4(0x80000000)
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bb.4.cond.end:
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%5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
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$rax = COPY %5(s64)
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RET 0, implicit $rax
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...
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---
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name: test_float
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: vecr, preferred-register: '' }
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- { id: 2, class: vecr, preferred-register: '' }
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- { id: 3, class: vecr, preferred-register: '' }
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- { id: 4, class: vecr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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- { id: 7, class: vecr, preferred-register: '' }
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- { id: 8, class: vecr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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; ALL-LABEL: name: test_float
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; ALL: bb.0.entry:
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; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; ALL: liveins: $edi, $xmm0, $xmm1
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
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; ALL: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
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; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
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; ALL: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
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; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
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; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
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; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
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; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
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; ALL: JCC_1 %bb.2, 5, implicit $eflags
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; ALL: bb.1.cond.false:
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; ALL: successors: %bb.2(0x80000000)
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; ALL: bb.2.cond.end:
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; ALL: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
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; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
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; ALL: $xmm0 = COPY [[COPY5]]
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; ALL: RET 0, implicit $xmm0
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bb.1.entry:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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liveins: $edi, $xmm0, $xmm1
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%0:gpr(s32) = COPY $edi
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%3:vecr(s128) = COPY $xmm0
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%1:vecr(s32) = G_TRUNC %3(s128)
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%4:vecr(s128) = COPY $xmm1
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%2:vecr(s32) = G_TRUNC %4(s128)
|
|
%5:gpr(s32) = G_CONSTANT i32 0
|
|
%9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
|
|
%6:gpr(s1) = G_TRUNC %9(s8)
|
|
G_BRCOND %6(s1), %bb.3
|
|
|
|
bb.2.cond.false:
|
|
successors: %bb.3(0x80000000)
|
|
|
|
bb.3.cond.end:
|
|
%7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
|
|
%8:vecr(s128) = G_ANYEXT %7(s32)
|
|
$xmm0 = COPY %8(s128)
|
|
RET 0, implicit $xmm0
|
|
|
|
...
|
|
---
|
|
name: test_double
|
|
alignment: 16
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
- { id: 1, class: vecr, preferred-register: '' }
|
|
- { id: 2, class: vecr, preferred-register: '' }
|
|
- { id: 3, class: vecr, preferred-register: '' }
|
|
- { id: 4, class: vecr, preferred-register: '' }
|
|
- { id: 5, class: gpr, preferred-register: '' }
|
|
- { id: 6, class: gpr, preferred-register: '' }
|
|
- { id: 7, class: vecr, preferred-register: '' }
|
|
- { id: 8, class: vecr, preferred-register: '' }
|
|
body: |
|
|
; ALL-LABEL: name: test_double
|
|
; ALL: bb.0.entry:
|
|
; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; ALL: liveins: $edi, $xmm0, $xmm1
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
|
|
; ALL: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
|
|
; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
|
|
; ALL: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
|
|
; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
|
|
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
|
|
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
|
|
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
|
|
; ALL: JCC_1 %bb.2, 5, implicit $eflags
|
|
; ALL: bb.1.cond.false:
|
|
; ALL: successors: %bb.2(0x80000000)
|
|
; ALL: bb.2.cond.end:
|
|
; ALL: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
|
|
; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
|
|
; ALL: $xmm0 = COPY [[COPY5]]
|
|
; ALL: RET 0, implicit $xmm0
|
|
bb.1.entry:
|
|
successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
|
liveins: $edi, $xmm0, $xmm1
|
|
|
|
%0:gpr(s32) = COPY $edi
|
|
%3:vecr(s128) = COPY $xmm0
|
|
%1:vecr(s64) = G_TRUNC %3(s128)
|
|
%4:vecr(s128) = COPY $xmm1
|
|
%2:vecr(s64) = G_TRUNC %4(s128)
|
|
%5:gpr(s32) = G_CONSTANT i32 0
|
|
%9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
|
|
%6:gpr(s1) = G_TRUNC %9(s8)
|
|
G_BRCOND %6(s1), %bb.3
|
|
|
|
bb.2.cond.false:
|
|
successors: %bb.3(0x80000000)
|
|
|
|
bb.3.cond.end:
|
|
%7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1
|
|
%8:vecr(s128) = G_ANYEXT %7(s64)
|
|
$xmm0 = COPY %8(s128)
|
|
RET 0, implicit $xmm0
|
|
|
|
...
|