59fa435ea6
This demonstrates a possible fix for PR48760 - for compares with constants, canonicalize the SGT/UGT condition code to use SGE/UGE which should reduce the number of EFLAGs bits we need to read. As discussed on PR48760, some EFLAG bits are treated independently which can require additional uops to merge together for certain CMOVcc/SETcc/etc. modes. I've limited this to cases where the constant increment doesn't result in a larger encoding or additional i64 constant materializations. Differential Revision: https://reviews.llvm.org/D101074
274 lines
7.7 KiB
LLVM
274 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -disable-cgp-select2branch -x86-cmov-converter=false | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: btl %esi, %edi
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; CHECK-NEXT: movl $12, %eax
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; CHECK-NEXT: cmovael (%rcx), %eax
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; CHECK-NEXT: retq
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entry:
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%0 = lshr i32 %x, %n
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%1 = and i32 %0, 1
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%toBool = icmp eq i32 %1, 0
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%v = load i32, i32* %vp
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%.0 = select i1 %toBool, i32 %v, i32 12
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ret i32 %.0
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}
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define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: btl %esi, %edi
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; CHECK-NEXT: movl $12, %eax
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; CHECK-NEXT: cmovbl (%rcx), %eax
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; CHECK-NEXT: retq
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entry:
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%0 = lshr i32 %x, %n
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%1 = and i32 %0, 1
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%toBool = icmp eq i32 %1, 0
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%v = load i32, i32* %vp
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%.0 = select i1 %toBool, i32 12, i32 %v
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ret i32 %.0
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}
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; x86's 32-bit cmov zeroes the high 32 bits of the destination. Make
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; sure CodeGen takes advantage of that to avoid an unnecessary
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; zero-extend (movl) after the cmov.
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declare void @bar(i64) nounwind
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define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: testb $1, %dl
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; CHECK-NEXT: cmovel %esi, %edi
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; CHECK-NEXT: callq bar@PLT
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: retq
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%c = trunc i64 %a to i32
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%d = trunc i64 %b to i32
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%e = select i1 %p, i32 %c, i32 %d
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%f = zext i32 %e to i64
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call void @bar(i64 %f)
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ret void
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}
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; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
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; move without recomputing EFLAGS, because the expansion of the conditional
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; move with control flow may clobber EFLAGS (e.g., with xor, to set the
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; register to zero).
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; The test is a little awkward; the important part is that there's a test before the
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; setne.
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; PR4814
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@g_3 = external dso_local global i8
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@g_96 = external dso_local global i8
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@g_100 = external dso_local global i8
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@_2E_str = external dso_local constant [15 x i8], align 1
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define i1 @test4() nounwind {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: movsbl g_3(%rip), %edx
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; CHECK-NEXT: movzbl %dl, %ecx
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; CHECK-NEXT: shrl $7, %ecx
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; CHECK-NEXT: xorb $1, %cl
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; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
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; CHECK-NEXT: sarl %cl, %edx
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; CHECK-NEXT: movb g_96(%rip), %al
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB3_2
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; CHECK-NEXT: # %bb.1: # %bb.i.i.i
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; CHECK-NEXT: movb g_100(%rip), %cl
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; CHECK-NEXT: .LBB3_2: # %func_4.exit.i
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; CHECK-NEXT: xorl %esi, %esi
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; CHECK-NEXT: testb %dl, %dl
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; CHECK-NEXT: setne %bl
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; CHECK-NEXT: movzbl %al, %ecx
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; CHECK-NEXT: cmovnel %esi, %ecx
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB3_5
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; CHECK-NEXT: # %bb.3: # %func_4.exit.i
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; CHECK-NEXT: testb %bl, %bl
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; CHECK-NEXT: jne .LBB3_5
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; CHECK-NEXT: # %bb.4: # %bb.i.i
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; CHECK-NEXT: movb g_100(%rip), %cl
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; CHECK-NEXT: xorl %ebx, %ebx
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: .LBB3_5: # %func_1.exit
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; CHECK-NEXT: movb %cl, g_96(%rip)
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; CHECK-NEXT: movzbl %cl, %esi
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; CHECK-NEXT: movl $_2E_str, %edi
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: callq printf@PLT
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; CHECK-NEXT: movl %ebx, %eax
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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entry:
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%0 = load i8, i8* @g_3, align 1
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%1 = sext i8 %0 to i32
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%.lobit.i = lshr i8 %0, 7
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%tmp.i = zext i8 %.lobit.i to i32
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%tmp.not.i = xor i32 %tmp.i, 1
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%iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i
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%retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8
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%2 = icmp eq i8 %retval56.i.i, 0
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%g_96.promoted.i = load i8, i8* @g_96
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%3 = icmp eq i8 %g_96.promoted.i, 0
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br i1 %3, label %func_4.exit.i, label %bb.i.i.i
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bb.i.i.i:
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%4 = load volatile i8, i8* @g_100, align 1
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br label %func_4.exit.i
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func_4.exit.i:
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%.not.i = xor i1 %2, true
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%brmerge.i = or i1 %3, %.not.i
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%.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0
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br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
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bb.i.i:
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%5 = load volatile i8, i8* @g_100, align 1
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br label %func_1.exit
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func_1.exit:
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%g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ]
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%ret = phi i1 [ 0, %bb.i.i ], [ %.not.i, %func_4.exit.i ]
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store i8 %g_96.tmp.0.i, i8* @g_96
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%6 = zext i8 %g_96.tmp.0.i to i32
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%7 = tail call i32 (i8*, ...) @printf(i8* noalias getelementptr ([15 x i8], [15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind
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ret i1 %ret
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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; Should compile to setcc | -2.
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; rdar://6668608
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define i32 @test5(i32* nocapture %P) nounwind readonly {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpl $42, (%rdi)
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; CHECK-NEXT: setge %al
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; CHECK-NEXT: orl $-2, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, i32* %P, align 4
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%1 = icmp sgt i32 %0, 41
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%iftmp.0.0 = select i1 %1, i32 -1, i32 -2
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ret i32 %iftmp.0.0
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}
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define i32 @test6(i32* nocapture %P) nounwind readonly {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpl $42, (%rdi)
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; CHECK-NEXT: setl %al
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; CHECK-NEXT: leal 4(%rax,%rax,8), %eax
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, i32* %P, align 4
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%1 = icmp sgt i32 %0, 41
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%iftmp.0.0 = select i1 %1, i32 4, i32 13
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ret i32 %iftmp.0.0
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}
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define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: cmovel %edx, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%d = select i1 %c, i8 %a, i8 %b
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ret i8 %d
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}
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define i64 @test8(i64 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: cmpq $-2147483648, %rdi # imm = 0x80000000
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; CHECK-NEXT: cmovlq %rdx, %rax
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; CHECK-NEXT: retq
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%4 = icmp sgt i64 %0, -2147483649
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%5 = select i1 %4, i64 %1, i64 %2
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ret i64 %5
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}
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define i32 @smin(i32 %x) {
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; CHECK-LABEL: smin:
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; CHECK: # %bb.0:
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; CHECK-NEXT: notl %edi
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovsl %edi, %eax
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; CHECK-NEXT: retq
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%not_x = xor i32 %x, -1
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%1 = icmp slt i32 %not_x, -1
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%sel = select i1 %1, i32 %not_x, i32 -1
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ret i32 %sel
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}
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define i32 @pr47049_1(i32 %0) {
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; CHECK-LABEL: pr47049_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmovlel %edi, %eax
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; CHECK-NEXT: retq
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%2 = icmp slt i32 %0, 1
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%3 = select i1 %2, i32 %0, i32 1
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ret i32 %3
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}
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define i32 @pr47049_2(i32 %0) {
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; CHECK-LABEL: pr47049_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovnsl %edi, %eax
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; CHECK-NEXT: retq
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%2 = icmp sgt i32 %0, -1
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%3 = select i1 %2, i32 %0, i32 -1
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ret i32 %3
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}
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define i32 @pr47049_3(i32 %0) {
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; CHECK-LABEL: pr47049_3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmovgl %edi, %eax
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; CHECK-NEXT: retq
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%2 = icmp sgt i32 %0, 1
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%3 = select i1 %2, i32 %0, i32 1
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ret i32 %3
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}
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define i32 @pr47049_4(i32 %0) {
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; CHECK-LABEL: pr47049_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmovnel %edi, %eax
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; CHECK-NEXT: retq
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%2 = icmp ugt i32 %0, 1
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%3 = select i1 %2, i32 %0, i32 1
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ret i32 %3
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}
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