0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
101 lines
3.0 KiB
LLVM
101 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -o - %s | FileCheck %s
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target triple = "i386-unknown-linux-gnu"
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@a = external dso_local global i32, align 4
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@d = external dso_local global i32*, align 4
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@k = external dso_local global i32**, align 4
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@j = external dso_local global i32***, align 4
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@h = external dso_local global i32, align 4
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@c = external dso_local global i32, align 4
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@i = external dso_local global i32, align 4
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@b = external dso_local global i32, align 4
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@f = external dso_local global i64, align 8
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@e = external dso_local global i64, align 8
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@g = external dso_local global i32, align 4
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declare i32 @fn1(i32 returned) optsize readnone
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declare i32 @main() optsize
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declare i32 @putchar(i32) nounwind
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define void @fn2() nounwind optsize {
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; CHECK-LABEL: fn2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl $48, (%esp)
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; CHECK-NEXT: calll putchar@PLT
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; CHECK-NEXT: movl h, %eax
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; CHECK-NEXT: movl c, %ecx
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; CHECK-NEXT: movl j, %edx
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; CHECK-NEXT: movl (%edx), %edx
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; CHECK-NEXT: movl (%edx), %edx
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; CHECK-NEXT: xorl %ebx, %ebx
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; CHECK-NEXT: cmpl (%edx), %ecx
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; CHECK-NEXT: setg %bl
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: cmpl %ebx, i
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; CHECK-NEXT: setg %cl
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; CHECK-NEXT: movl %ecx, b
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: cmpl %ecx, %eax
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; CHECK-NEXT: setg %dl
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; CHECK-NEXT: xorl %edx, a
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; CHECK-NEXT: movl d, %eax
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; CHECK-NEXT: movl (%eax), %eax
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; CHECK-NEXT: andl %eax, e
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: andl %eax, e+4
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; CHECK-NEXT: decl g
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; CHECK-NEXT: addl $1, f
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; CHECK-NEXT: adcl $0, f+4
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; CHECK-NEXT: addl $8, %esp
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: retl
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entry:
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%putchar = tail call i32 @putchar(i32 48)
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%0 = load volatile i32, i32* @h, align 4
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%1 = load i32, i32* @c, align 4, !tbaa !1
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%2 = load i32***, i32**** @j, align 4
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%3 = load i32**, i32*** %2, align 4
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%4 = load i32*, i32** %3, align 4
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%5 = load i32, i32* %4, align 4
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%cmp = icmp sgt i32 %1, %5
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%conv = zext i1 %cmp to i32
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%6 = load i32, i32* @i, align 4
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%cmp1 = icmp sgt i32 %6, %conv
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%conv2 = zext i1 %cmp1 to i32
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store i32 %conv2, i32* @b, align 4
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%cmp3 = icmp sgt i32 %0, %conv2
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%conv4 = zext i1 %cmp3 to i32
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%7 = load i32, i32* @a, align 4
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%or = xor i32 %7, %conv4
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store i32 %or, i32* @a, align 4
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%8 = load i32*, i32** @d, align 4
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%9 = load i32, i32* %8, align 4
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%conv6 = sext i32 %9 to i64
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%10 = load i64, i64* @e, align 8
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%and = and i64 %10, %conv6
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store i64 %and, i64* @e, align 8
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%11 = load i32, i32* @g, align 4
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%dec = add nsw i32 %11, -1
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store i32 %dec, i32* @g, align 4
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%12 = load i64, i64* @f, align 8
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%inc = add nsw i64 %12, 1
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store i64 %inc, i64* @f, align 8
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ret void
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}
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!0 = !{i32 1, !"NumRegisterParameters", i32 0}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!6, !6, i64 0}
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!6 = !{!"any pointer", !3, i64 0}
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!7 = !{!8, !8, i64 0}
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!8 = !{!"long long", !3, i64 0}
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