2cbf9fd402
IR typically creates INSERT_SUBVECTOR patterns as a widening of the subvector with undefs to pad to the destination size, followed by a shuffle for the actual insertion - SelectionDAGBuilder has to do something similar for shuffles when source/destination vectors are different sizes. This combine attempts to recognize these patterns by looking for a shuffle of a subvector (from a CONCAT_VECTORS) that starts at a modulo of its size into an otherwise identity shuffle of the base vector. This uncovered a couple of target-specific issues as we haven't often created INSERT_SUBVECTOR nodes in generic code - aarch64 could only handle insertions into the bottom of undefs (i.e. a vector widening), and x86-avx512 vXi1 insertion wasn't keeping track of undef elements in the base vector. Fixes PR50053 Differential Revision: https://reviews.llvm.org/D107068
61 lines
3.5 KiB
LLVM
61 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 -O0 | FileCheck %s
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define <16 x i64> @pluto(<16 x i64> %arg, <16 x i64> %arg1, <16 x i64> %arg2, <16 x i64> %arg3, <16 x i64> %arg4) {
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; CHECK-LABEL: pluto:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK-NEXT: .cfi_def_cfa_register %rbp
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; CHECK-NEXT: andq $-32, %rsp
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; CHECK-NEXT: subq $32, %rsp
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; CHECK-NEXT: vmovaps %ymm4, %ymm10
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; CHECK-NEXT: vmovaps %ymm3, %ymm9
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; CHECK-NEXT: vmovaps %ymm1, %ymm8
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; CHECK-NEXT: vmovaps %ymm0, %ymm4
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; CHECK-NEXT: vmovaps 240(%rbp), %ymm1
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; CHECK-NEXT: vmovaps 208(%rbp), %ymm3
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; CHECK-NEXT: vmovaps 176(%rbp), %ymm0
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; CHECK-NEXT: vmovaps 144(%rbp), %ymm0
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; CHECK-NEXT: vmovaps 112(%rbp), %ymm11
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; CHECK-NEXT: vmovaps 80(%rbp), %ymm11
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; CHECK-NEXT: vmovaps 48(%rbp), %ymm11
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; CHECK-NEXT: vmovaps 16(%rbp), %ymm11
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; CHECK-NEXT: vpblendd {{.*#+}} ymm4 = ymm6[0,1,2,3,4,5],ymm2[6,7]
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; CHECK-NEXT: vmovaps %xmm3, %xmm6
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; CHECK-NEXT: # implicit-def: $ymm2
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; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm2, %ymm2
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; CHECK-NEXT: vpalignr {{.*#+}} ymm0 = ymm4[8,9,10,11,12,13,14,15],ymm0[0,1,2,3,4,5,6,7],ymm4[24,25,26,27,28,29,30,31],ymm0[16,17,18,19,20,21,22,23]
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; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,0]
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; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5],ymm0[6,7]
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; CHECK-NEXT: vextracti128 $1, %ymm7, %xmm2
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; CHECK-NEXT: vmovq {{.*#+}} xmm6 = xmm2[0],zero
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; CHECK-NEXT: # implicit-def: $ymm2
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; CHECK-NEXT: vmovaps %xmm6, %xmm2
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; CHECK-NEXT: # kill: def $xmm4 killed $xmm4 killed $ymm4
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; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm2, %ymm2
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; CHECK-NEXT: vmovaps %xmm7, %xmm4
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; CHECK-NEXT: vpslldq {{.*#+}} xmm6 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
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; CHECK-NEXT: # implicit-def: $ymm4
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; CHECK-NEXT: vmovaps %xmm6, %xmm4
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; CHECK-NEXT: vpalignr {{.*#+}} ymm3 = ymm3[8,9,10,11,12,13,14,15],ymm5[0,1,2,3,4,5,6,7],ymm3[24,25,26,27,28,29,30,31],ymm5[16,17,18,19,20,21,22,23]
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; CHECK-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,0,3]
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; CHECK-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7]
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; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm7[0,1],ymm1[2,3],ymm7[4,5,6,7]
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; CHECK-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,1,1,3]
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; CHECK-NEXT: vpshufd {{.*#+}} ymm4 = ymm5[0,1,0,1,4,5,4,5]
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; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm4[6,7]
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; CHECK-NEXT: movq %rbp, %rsp
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa %rsp, 8
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; CHECK-NEXT: retq
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bb:
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%tmp = select <16 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <16 x i64> %arg, <16 x i64> %arg1
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%tmp5 = select <16 x i1> <i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x i64> %arg2, <16 x i64> zeroinitializer
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%tmp6 = select <16 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true>, <16 x i64> %arg3, <16 x i64> %tmp5
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%tmp7 = shufflevector <16 x i64> %tmp, <16 x i64> %tmp6, <16 x i32> <i32 11, i32 18, i32 24, i32 9, i32 14, i32 29, i32 29, i32 6, i32 14, i32 28, i32 8, i32 9, i32 22, i32 12, i32 25, i32 6>
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ret <16 x i64> %tmp7
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}
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