13b4db4ec2
Since we're messing with individual element loads we need to expose this to show whats going on. Part of the work to fix the masked_expandload.ll regressions in D66004
38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_mem_shuffle
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s
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define <2 x i64> @test5(i64* %base, <2 x i64> %src0) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpinsrq $1, (%rdi), %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x i64> @llvm.masked.expandload.v2i64(i64* %base, <2 x i1> <i1 false, i1 true>, <2 x i64> %src0)
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ret <2 x i64>%res
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}
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declare <2 x i64> @llvm.masked.expandload.v2i64(i64*, <2 x i1>, <2 x i64>)
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define void @test11(i64* %base, <2 x i64> %V, <2 x i1> %mask) {
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; CHECK-LABEL: test11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm1, %xmm1
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; CHECK-NEXT: vmovmskpd %xmm1, %eax
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; CHECK-NEXT: testb $1, %al
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; CHECK-NEXT: jne .LBB1_1
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; CHECK-NEXT: # %bb.2: # %else
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; CHECK-NEXT: testb $2, %al
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; CHECK-NEXT: jne .LBB1_3
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; CHECK-NEXT: .LBB1_4: # %else2
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_1: # %cond.store
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; CHECK-NEXT: vmovq %xmm0, (%rdi)
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; CHECK-NEXT: addq $8, %rdi
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; CHECK-NEXT: testb $2, %al
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; CHECK-NEXT: je .LBB1_4
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; CHECK-NEXT: .LBB1_3: # %cond.store1
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; CHECK-NEXT: vpextrq $1, %xmm0, (%rdi)
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; CHECK-NEXT: retq
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call void @llvm.masked.compressstore.v2i64(<2 x i64> %V, i64* %base, <2 x i1> %mask)
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ret void
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}
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declare void @llvm.masked.compressstore.v2i64(<2 x i64>, i64* , <2 x i1>)
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