Files
clang-p2996/llvm/test/CodeGen/X86/pr41619.ll
Eli Friedman bdd55b2f18 Fix the default alignment of i1 vectors.
Currently, the default alignment is much larger than the actual size of
the vector in memory.  Fix this to use a sane default.

For SVE, temporarily remove lowering of load/store operations for
predicates with less than 16 elements. The layout the backend was
assuming for SVE predicates with less than 16 elements doesn't agree
with the frontend. More work probably needs to be done here.

This change is, strictly speaking, not backwards-compatible at the
bitcode level. But probably nobody is actually depending on that; i1
vectors in memory are rare, and the code that does use them probably
ends up forcing the alignment to something sane anyway.  If we think
this is a concern, I can restrict this to scalable vectors for now
(where it's actually causing issues for me at the moment).

Differential Revision: https://reviews.llvm.org/D88994
2021-07-31 14:09:59 -07:00

45 lines
2.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.14.0 -mattr=avx2 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.14.0 -mattr=avx512bw | FileCheck %s --check-prefixes=CHECK
define void @foo(double %arg) {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %bb
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: vmovd %eax, %xmm0
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: movl %eax, (%rax)
; CHECK-NEXT: vmovlps %xmm1, (%rax)
; CHECK-NEXT: retq
bb:
%tmp = bitcast double %arg to i64
%tmp1 = trunc i64 %tmp to i32
%tmp2 = bitcast i32 %tmp1 to float
%tmp3 = insertelement <4 x float> zeroinitializer, float %tmp2, i32 2
%tmp4 = bitcast <4 x float> %tmp3 to <2 x double>
%tmp5 = extractelement <2 x double> %tmp4, i32 0
%tmp6 = extractelement <2 x double> %tmp4, i32 1
%tmp7 = bitcast double %tmp6 to i64
%tmp8 = trunc i64 %tmp7 to i32
store i32 %tmp8, i32* undef, align 4
store double %tmp5, double* undef, align 16
ret void
}
; This used to crash with mask registers on avx512bw targets.
define i32 @bar(double %blah) nounwind {
; CHECK-LABEL: bar:
; CHECK: ## %bb.0:
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: ## kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
%z = bitcast double %blah to i64
%y = trunc i64 %z to i32
%a = bitcast i32 %y to <32 x i1>
%b = shufflevector <32 x i1> %a, <32 x i1> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%c = bitcast <64 x i1> %b to i64
%d = trunc i64 %c to i32
ret i32 %d
}