5609c8b607
This patch transforms the sequence
lea (reg1, reg2), reg3
sub reg3, reg4
to two sub instructions
sub reg1, reg4
sub reg2, reg4
Similar optimization can also be applied to LEA/ADD sequence.
The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register
of ADD).
Differential Revision: https://reviews.llvm.org/D104684
156 lines
6.8 KiB
LLVM
156 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vp2intersect -verify-machineinstrs | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vp2intersect -verify-machineinstrs | FileCheck %s --check-prefix=X64
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; Test with more than four live mask pairs
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define void @test(<16 x i32> %a0, <16 x i32> %b0, <16 x i32> %a1, <16 x i32> %b1, <16 x i32> %a2, <16 x i32> %b2, <16 x i32> %a3, <16 x i32> %b3, <16 x i32> %a4, <16 x i32> %b4, i16* nocapture %m0, i16* nocapture %m1) nounwind {
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; X86-LABEL: test:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: andl $-64, %esp
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; X86-NEXT: subl $64, %esp
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; X86-NEXT: movl 456(%ebp), %esi
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; X86-NEXT: vmovaps 328(%ebp), %zmm3
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; X86-NEXT: vmovaps 200(%ebp), %zmm4
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; X86-NEXT: vmovaps 72(%ebp), %zmm5
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; X86-NEXT: vp2intersectd %zmm1, %zmm0, %k0
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; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: vp2intersectd 8(%ebp), %zmm2, %k0
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; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: vp2intersectd 136(%ebp), %zmm5, %k0
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; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: vp2intersectd 264(%ebp), %zmm4, %k0
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; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: vp2intersectd 392(%ebp), %zmm3, %k0
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; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: kmovw %k1, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
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; X86-NEXT: vzeroupper
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; X86-NEXT: calll dummy@PLT
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 2-byte Reload
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k1 # 2-byte Reload
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; X86-NEXT: kmovw %k0, %eax
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 2-byte Reload
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k1 # 2-byte Reload
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; X86-NEXT: kmovw %k0, %ecx
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 2-byte Reload
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k1 # 2-byte Reload
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; X86-NEXT: kmovw %k0, %edx
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 2-byte Reload
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k1 # 2-byte Reload
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; X86-NEXT: kmovw %k0, %edi
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; X86-NEXT: addl %edi, %eax
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k2 # 2-byte Reload
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; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k3 # 2-byte Reload
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; X86-NEXT: kmovw %k2, %edi
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; X86-NEXT: addl %ecx, %edx
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; X86-NEXT: kmovw %k1, %ecx
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; X86-NEXT: addl %edi, %ecx
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: addl %edx, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: leal -8(%ebp), %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: test:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rbp
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; X64-NEXT: movq %rsp, %rbp
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; X64-NEXT: pushq %r14
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; X64-NEXT: pushq %rbx
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; X64-NEXT: andq $-64, %rsp
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; X64-NEXT: subq $64, %rsp
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; X64-NEXT: movq %rdi, %r14
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; X64-NEXT: vmovaps 16(%rbp), %zmm8
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; X64-NEXT: vp2intersectd %zmm1, %zmm0, %k0
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; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: vp2intersectd %zmm3, %zmm2, %k0
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; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: vp2intersectd %zmm5, %zmm4, %k0
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; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: vp2intersectd %zmm7, %zmm6, %k0
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; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: vp2intersectd 80(%rbp), %zmm8, %k0
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; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; X64-NEXT: vzeroupper
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; X64-NEXT: callq dummy@PLT
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
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; X64-NEXT: kmovw %k0, %eax
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
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; X64-NEXT: kmovw %k0, %ecx
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
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; X64-NEXT: kmovw %k0, %edx
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
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; X64-NEXT: kmovw %k0, %esi
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
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; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
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; X64-NEXT: kmovw %k0, %edi
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; X64-NEXT: kmovw %k1, %ebx
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; X64-NEXT: addl %edi, %eax
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; X64-NEXT: addl %ecx, %edx
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; X64-NEXT: addl %ebx, %eax
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; X64-NEXT: addl %esi, %eax
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; X64-NEXT: addl %edx, %eax
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; X64-NEXT: movw %ax, (%r14)
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; X64-NEXT: leaq -16(%rbp), %rsp
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; X64-NEXT: popq %rbx
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; X64-NEXT: popq %r14
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; X64-NEXT: popq %rbp
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; X64-NEXT: retq
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entry:
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%0 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a0, <16 x i32> %b0)
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%1 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a1, <16 x i32> %b1)
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%2 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a2, <16 x i32> %b2)
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%3 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a3, <16 x i32> %b3)
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%4 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a4, <16 x i32> %b4)
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%5 = extractvalue { <16 x i1>, <16 x i1> } %0, 0
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%6 = extractvalue { <16 x i1>, <16 x i1> } %1, 0
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%7 = extractvalue { <16 x i1>, <16 x i1> } %2, 0
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%8 = extractvalue { <16 x i1>, <16 x i1> } %3, 0
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%9 = extractvalue { <16 x i1>, <16 x i1> } %4, 0
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%10 = extractvalue { <16 x i1>, <16 x i1> } %0, 1
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%11 = extractvalue { <16 x i1>, <16 x i1> } %1, 1
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call void @dummy()
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%12 = bitcast <16 x i1> %5 to i16
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%13 = bitcast <16 x i1> %6 to i16
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%14 = bitcast <16 x i1> %7 to i16
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%15 = bitcast <16 x i1> %8 to i16
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%16 = bitcast <16 x i1> %9 to i16
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%17 = bitcast <16 x i1> %10 to i16
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%18 = bitcast <16 x i1> %11 to i16
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%19 = add i16 %12, %13
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%20 = add i16 %14, %15
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%21 = add i16 %16, %17
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%22 = add i16 %19, %21
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%23 = add i16 %22, %20
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store i16 %23, i16* %m0, align 16
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ret void
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}
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declare { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32>, <16 x i32>)
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declare void @dummy()
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