69a3acffdf
This patch demonstrates a scenario when we need to load/store a single 64-byte value, which is done by 2 ymm loads and stores in AVX. The current codegen choses the following sequence: load ymm0 load ymm1 store ymm1 store ymm0 If we instead stored ymm0 before ymm1, we could execute 2nd load and 1st store in parallel.
22 lines
767 B
LLVM
22 lines
767 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx | FileCheck %s
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; TODO: We If we stored ymm0 before ymm1, then we could execute 2nd load and 1st store in
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; parallel.
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define void @test_01(i8* %src, i8* %dest) {
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; CHECK-LABEL: test_01:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmovups (%rdi), %ymm0
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; CHECK-NEXT: vmovups 32(%rdi), %ymm1
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; CHECK-NEXT: vmovups %ymm1, 32(%rsi)
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; CHECK-NEXT: vmovups %ymm0, (%rsi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%read = bitcast i8* %src to <64 x i8>*
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%value = load <64 x i8>, <64 x i8>* %read, align 1
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%write = bitcast i8* %dest to <64 x i8>*
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store <64 x i8> %value, <64 x i8>* %write, align 1
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ret void
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}
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