9ce5f41851
As discussed in PR42696: https://bugs.llvm.org/show_bug.cgi?id=42696 ...but won't help that case yet. We have an odd situation where a select operand equivalence fold was implemented in InstSimplify when it could have been done more generally in InstCombine if we allow dropping of {nsw,nuw,exact} from a binop operand. Here's an example: https://rise4fun.com/Alive/Xplr %cmp = icmp eq i32 %x, 2147483647 %add = add nsw i32 %x, 1 %sel = select i1 %cmp, i32 -2147483648, i32 %add => %sel = add i32 %x, 1 I've left the InstSimplify code in place for now, but my guess is that we'd prefer to remove that as a follow-up to save on code duplication and compile-time. Differential Revision: https://reviews.llvm.org/D65576 llvm-svn: 367695
106 lines
3.5 KiB
LLVM
106 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -instcombine < %s | FileCheck %s
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define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, 15
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%2 = shl nuw nsw i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %1, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_shl_of_true_val2(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, 15
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%2 = shl nuw nsw i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %2, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, 60
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%2 = lshr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %1, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_lshr_of_true_val2(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, 60
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%2 = lshr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %2, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, -2147483588
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%2 = ashr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %1, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, -2147483588
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%2 = ashr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %2, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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