23c2f2e6b2
This patch marks the induction increment of the main induction variable of the vector loop as NUW when not folding the tail. If the tail is not folded, we know that End - Start >= Step (either statically or through the minimum iteration checks). We also know that both Start % Step == 0 and End % Step == 0. We exit the vector loop if %IV + %Step == %End. Hence we must exit the loop before %IV + %Step unsigned overflows and we can mark the induction increment as NUW. This should make SCEV return more precise bounds for the created vector loops, used by later optimizations, like late unrolling. At the moment quite a few tests still need to be updated, but before doing so I'd like to get initial feedback to make sure I am not missing anything. Note that this could probably be further improved by using information from the original IV. Attempt of modeling of the assumption in Alive2: https://alive2.llvm.org/ce/z/H_DL_g Part of a set of fixes required for PR50412. Reviewed By: mkazantsev Differential Revision: https://reviews.llvm.org/D103255
110 lines
5.9 KiB
LLVM
110 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -S | FileCheck %s
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; Test case for PR44488. Checks that the correct predicates are created for
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; branches where true and false successors are equal. See the checks involving
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; CMP1 and CMP2.
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@v_38 = global i16 12061, align 1
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@v_39 = global i16 11333, align 1
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define i16 @test_true_and_false_branch_equal() {
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; CHECK-LABEL: @test_true_and_false_branch_equal(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE4:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 99, [[TMP0]]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[OFFSET_IDX]], i32 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], <i16 0, i16 1>
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; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = load i16, i16* @v_38, align 1
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i32 0
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; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT1]], <2 x i16> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i16> [[BROADCAST_SPLAT2]], <i16 32767, i16 32767>
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i16> [[BROADCAST_SPLAT2]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i1> [[TMP4]], <i1 true, i1 true>
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i32 0
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; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]]
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; CHECK: pred.srem.if:
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; CHECK-NEXT: [[TMP7:%.*]] = srem i16 5786, [[TMP2]]
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i16> poison, i16 [[TMP7]], i32 0
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; CHECK-NEXT: br label [[PRED_SREM_CONTINUE]]
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; CHECK: pred.srem.continue:
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; CHECK-NEXT: [[TMP9:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP8]], [[PRED_SREM_IF]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1
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; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_SREM_IF3:%.*]], label [[PRED_SREM_CONTINUE4]]
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; CHECK: pred.srem.if3:
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; CHECK-NEXT: [[TMP11:%.*]] = srem i16 5786, [[TMP2]]
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; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i16> [[TMP9]], i16 [[TMP11]], i32 1
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; CHECK-NEXT: br label [[PRED_SREM_CONTINUE4]]
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; CHECK: pred.srem.continue4:
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; CHECK-NEXT: [[TMP13:%.*]] = phi <2 x i16> [ [[TMP9]], [[PRED_SREM_CONTINUE]] ], [ [[TMP12]], [[PRED_SREM_IF3]] ]
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP4]], <2 x i16> <i16 5786, i16 5786>, <2 x i16> [[TMP13]]
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; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 0
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; CHECK-NEXT: store i16 [[TMP14]], i16* @v_39, align 1
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 1
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; CHECK-NEXT: store i16 [[TMP15]], i16* @v_39, align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12
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; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 12, 12
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 111, [[MIDDLE_BLOCK]] ], [ 99, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_07:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC7:%.*]], [[FOR_LATCH:%.*]] ]
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; CHECK-NEXT: [[LV:%.*]] = load i16, i16* @v_38, align 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i16 [[LV]], 32767
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; CHECK-NEXT: br i1 [[CMP1]], label [[COND_END:%.*]], label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i16 [[LV]], 0
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; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_LATCH]], label [[COND_FALSE4:%.*]]
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; CHECK: cond.false4:
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; CHECK-NEXT: [[REM:%.*]] = srem i16 5786, [[LV]]
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; CHECK-NEXT: br label [[FOR_LATCH]]
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; CHECK: for.latch:
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; CHECK-NEXT: [[COND6:%.*]] = phi i16 [ [[REM]], [[COND_FALSE4]] ], [ 5786, [[COND_END]] ]
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; CHECK-NEXT: store i16 [[COND6]], i16* @v_39, align 1
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; CHECK-NEXT: [[INC7]] = add nsw i16 [[I_07]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC7]], 111
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], [[LOOP2:!llvm.loop !.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[RV:%.*]] = load i16, i16* @v_39, align 1
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; CHECK-NEXT: ret i16 [[RV]]
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.latch
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%i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ]
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%lv = load i16, i16* @v_38, align 1
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%cmp1 = icmp eq i16 %lv, 32767
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br i1 %cmp1, label %cond.end, label %cond.end
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cond.end: ; preds = %for.body, %for.body
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%cmp2 = icmp eq i16 %lv, 0
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br i1 %cmp2, label %for.latch, label %cond.false4
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cond.false4: ; preds = %cond.end
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%rem = srem i16 5786, %lv
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br label %for.latch
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for.latch: ; preds = %cond.end, %cond.false4
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%cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ]
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store i16 %cond6, i16* @v_39, align 1
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%inc7 = add nsw i16 %i.07, 1
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%cmp = icmp slt i16 %inc7, 111
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br i1 %cmp, label %for.body, label %exit
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exit: ; preds = %for.latch
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%rv = load i16, i16* @v_39, align 1
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ret i16 %rv
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}
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