4a8e6ed2f7
This patch makes SLP and LV emit operations with initial vectors set to poison constant instead of undef. This is a part of efforts for using poison vector instead of undef to represent "doesn't care" vector. The goal is to make nice shufflevector optimizations valid that is currently incorrect due to the tricky interaction between undef and poison (see https://bugs.llvm.org/show_bug.cgi?id=44185 ). Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D94061
70 lines
3.0 KiB
LLVM
70 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake < %s | FileCheck %s
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define void @mainTest(i32 %param, i32 * %vals, i32 %len) {
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; CHECK-LABEL: @mainTest(
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; CHECK-NEXT: bci_15.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 31, i32 poison>, i32 [[PARAM:%.*]], i32 1
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; CHECK-NEXT: br label [[BCI_15:%.*]]
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; CHECK: bci_15:
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; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ [[TMP7:%.*]], [[BCI_15]] ], [ [[TMP0]], [[BCI_15_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1>
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i32> [[SHUFFLE]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <16 x i32> [[SHUFFLE]], i32 15
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; CHECK-NEXT: store atomic i32 [[TMP3]], i32* [[VALS:%.*]] unordered, align 4
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; CHECK-NEXT: [[TMP4:%.*]] = add <16 x i32> [[SHUFFLE]], <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 -1>
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; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> [[TMP4]])
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; CHECK-NEXT: [[OP_EXTRA:%.*]] = and i32 [[TMP5]], [[TMP2]]
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; CHECK-NEXT: [[V44:%.*]] = add i32 [[TMP2]], 16
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[V44]], i32 0
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; CHECK-NEXT: [[TMP7]] = insertelement <2 x i32> [[TMP6]], i32 [[OP_EXTRA]], i32 1
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; CHECK-NEXT: br i1 true, label [[BCI_15]], label [[LOOPEXIT:%.*]]
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; CHECK: loopexit:
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; CHECK-NEXT: ret void
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;
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bci_15.preheader:
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br label %bci_15
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bci_15: ; preds = %bci_15.preheader, %bci_15
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%local_0_ = phi i32 [ %v43, %bci_15 ], [ %param, %bci_15.preheader ]
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%local_4_ = phi i32 [ %v44, %bci_15 ], [ 31, %bci_15.preheader ]
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%v12 = add i32 %local_0_, -1
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store atomic i32 %local_0_, i32 * %vals unordered, align 4
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%v13 = add i32 %local_4_, 1
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%v14 = and i32 %local_4_, %v12
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%v15 = add i32 %local_4_, 2
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%v16 = and i32 %v13, %v14
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%v17 = add i32 %local_4_, 3
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%v18 = and i32 %v15, %v16
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%v19 = add i32 %local_4_, 4
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%v20 = and i32 %v17, %v18
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%v21 = add i32 %local_4_, 5
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%v22 = and i32 %v19, %v20
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%v23 = add i32 %local_4_, 6
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%v24 = and i32 %v21, %v22
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%v25 = add i32 %local_4_, 7
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%v26 = and i32 %v23, %v24
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%v27 = add i32 %local_4_, 8
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%v28 = and i32 %v25, %v26
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%v29 = add i32 %local_4_, 9
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%v30 = and i32 %v27, %v28
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%v31 = add i32 %local_4_, 10
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%v32 = and i32 %v29, %v30
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%v33 = add i32 %local_4_, 11
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%v34 = and i32 %v31, %v32
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%v35 = add i32 %local_4_, 12
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%v36 = and i32 %v33, %v34
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%v37 = add i32 %local_4_, 13
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%v38 = and i32 %v35, %v36
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%v39 = add i32 %local_4_, 14
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%v40 = and i32 %v37, %v38
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%v41 = add i32 %local_4_, 15
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%v42 = and i32 %v39, %v40
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%v43 = and i32 %v41, %v42
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%v44 = add i32 %local_4_, 16
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br i1 true, label %bci_15, label %loopexit
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loopexit:
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ret void
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}
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