Files
clang-p2996/llvm/utils/TableGen
Christudasan Devadasan 6a75041a16 [TableGen] Allow target specific flags for RegisterClass
Analogous to the TSFlags for machine instructions, this
patch introduces a bit vector for register classes to have
target specific flags that become a tablegened value in
TargetRegisterClass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D108767
2021-08-31 22:29:11 -04:00
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