f137c3d592
This avoids doing a Triple -> std::string -> Triple round trip in lots of places, now that the Module stores a Triple.
246 lines
9.1 KiB
C++
246 lines
9.1 KiB
C++
//===- llvm/unittests/MC/AMDGPU/PALMetadata.cpp ---------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "GCNSubtarget.h"
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#include "SIProgramInfo.h"
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#include "Utils/AMDGPUPALMetadata.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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class PALMetadata : public testing::Test {
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protected:
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std::unique_ptr<GCNTargetMachine> TM;
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std::unique_ptr<LLVMContext> Ctx;
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std::unique_ptr<GCNSubtarget> ST;
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std::unique_ptr<MachineModuleInfo> MMI;
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std::unique_ptr<MachineFunction> MF;
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std::unique_ptr<Module> M;
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AMDGPUPALMetadata MD;
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static void SetUpTestSuite() {
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LLVMInitializeAMDGPUTargetInfo();
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LLVMInitializeAMDGPUTarget();
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LLVMInitializeAMDGPUTargetMC();
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}
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PALMetadata() {
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Triple TT("amdgcn--amdpal");
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StringRef CPU = "gfx1010";
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StringRef FS = "";
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std::string Error;
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const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
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TargetOptions Options;
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TM.reset(static_cast<GCNTargetMachine *>(TheTarget->createTargetMachine(
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TT, CPU, FS, Options, std::nullopt, std::nullopt)));
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Ctx = std::make_unique<LLVMContext>();
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M = std::make_unique<Module>("Module", *Ctx);
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M->setDataLayout(TM->createDataLayout());
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auto *FType = FunctionType::get(Type::getVoidTy(*Ctx), false);
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auto *F = Function::Create(FType, GlobalValue::ExternalLinkage, "Test", *M);
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MMI = std::make_unique<MachineModuleInfo>(TM.get());
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ST = std::make_unique<GCNSubtarget>(TM->getTargetTriple(),
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TM->getTargetCPU(),
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TM->getTargetFeatureString(), *TM);
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MF = std::make_unique<MachineFunction>(*F, *TM, *ST, MMI->getContext(), 1);
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}
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};
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TEST_F(PALMetadata, ResourceRegisterSetORsResolvableUnknown) {
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StringRef yaml = "---\n"
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"amdpal.pipelines:\n"
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" - .hardware_stages:\n"
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" .es:\n"
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" .entry_point: Test\n"
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" .scratch_memory_size: 0\n"
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" .sgpr_count: 0x1\n"
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" .vgpr_count: 0x1\n"
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" .registers:\n"
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" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
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" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
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"...\n";
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MCContext &MCCtx = MF->getContext();
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auto CC = CallingConv::AMDGPU_VS;
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MD.setFromString(yaml);
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MD.setRsrc2(CC, MCConstantExpr::create(42, MCCtx), MCCtx);
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MCSymbol *Sym = MCCtx.getOrCreateSymbol("Unknown");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(Sym, MCCtx), MCCtx);
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EXPECT_FALSE(MD.resolvedAllMCExpr());
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MD.setRsrc2(CC, MCConstantExpr::create(0xff00, MCCtx), MCCtx);
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Sym->setVariableValue(MCConstantExpr::create(0xffff0000, MCCtx));
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std::string Output;
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MD.toString(Output);
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EXPECT_TRUE(MD.resolvedAllMCExpr());
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auto n = Output.find("\'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0xffffff2a");
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EXPECT_TRUE(n != std::string::npos);
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}
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TEST_F(PALMetadata, ResourceRegisterSetORsResolvableUnknowns) {
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StringRef yaml = "---\n"
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"amdpal.pipelines:\n"
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" - .hardware_stages:\n"
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" .es:\n"
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" .entry_point: Test\n"
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" .scratch_memory_size: 0\n"
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" .sgpr_count: 0x1\n"
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" .vgpr_count: 0x1\n"
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" .registers:\n"
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" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
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" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
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"...\n";
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MCContext &MCCtx = MF->getContext();
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auto CC = CallingConv::AMDGPU_VS;
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MD.setFromString(yaml);
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MCSymbol *SymOne = MCCtx.getOrCreateSymbol("UnknownOne");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(SymOne, MCCtx), MCCtx);
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MD.setRsrc2(CC, MCConstantExpr::create(42, MCCtx), MCCtx);
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MCSymbol *SymTwo = MCCtx.getOrCreateSymbol("UnknownTwo");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(SymTwo, MCCtx), MCCtx);
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EXPECT_FALSE(MD.resolvedAllMCExpr());
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SymOne->setVariableValue(MCConstantExpr::create(0xffff0000, MCCtx));
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SymTwo->setVariableValue(MCConstantExpr::create(0x0000ff00, MCCtx));
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std::string Output;
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MD.toString(Output);
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EXPECT_TRUE(MD.resolvedAllMCExpr());
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auto n = Output.find("\'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0xffffff2a");
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EXPECT_TRUE(n != std::string::npos);
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}
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TEST_F(PALMetadata, ResourceRegisterSetORsPreset) {
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StringRef yaml = "---\n"
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"amdpal.pipelines:\n"
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" - .hardware_stages:\n"
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" .es:\n"
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" .entry_point: Test\n"
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" .scratch_memory_size: 0\n"
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" .sgpr_count: 0x1\n"
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" .vgpr_count: 0x1\n"
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" .registers:\n"
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" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
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" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0x2a\n"
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"...\n";
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MCContext &MCCtx = MF->getContext();
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auto CC = CallingConv::AMDGPU_VS;
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MD.setFromString(yaml);
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MCSymbol *Sym = MCCtx.getOrCreateSymbol("Unknown");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(Sym, MCCtx), MCCtx);
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MD.setRsrc2(CC, MCConstantExpr::create(0xff00, MCCtx), MCCtx);
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Sym->setVariableValue(MCConstantExpr::create(0xffff0000, MCCtx));
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std::string Output;
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MD.toString(Output);
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auto n = Output.find("\'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0xffffff2a");
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EXPECT_TRUE(n != std::string::npos);
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}
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TEST_F(PALMetadata, ResourceRegisterSetORs) {
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StringRef yaml = "---\n"
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"amdpal.pipelines:\n"
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" - .hardware_stages:\n"
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" .es:\n"
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" .entry_point: Test\n"
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" .scratch_memory_size: 0\n"
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" .sgpr_count: 0x1\n"
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" .vgpr_count: 0x1\n"
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" .registers:\n"
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" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
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" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
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"...\n";
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MCContext &MCCtx = MF->getContext();
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auto CC = CallingConv::AMDGPU_VS;
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MD.setFromString(yaml);
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MCSymbol *Sym = MCCtx.getOrCreateSymbol("Unknown");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(Sym, MCCtx), MCCtx);
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MD.setRsrc2(CC, 42);
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MD.setRsrc2(CC, MCConstantExpr::create(0xff00, MCCtx), MCCtx);
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Sym->setVariableValue(MCConstantExpr::create(0xffff0000, MCCtx));
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std::string Output;
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MD.toString(Output);
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auto n = Output.find("\'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0xffffff2a");
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EXPECT_TRUE(n != std::string::npos);
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}
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TEST_F(PALMetadata, ResourceRegisterSetUnresolvedSym) {
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StringRef yaml = "---\n"
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"amdpal.pipelines:\n"
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" - .hardware_stages:\n"
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" .es:\n"
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" .entry_point: Test\n"
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" .scratch_memory_size: 0\n"
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" .sgpr_count: 0x1\n"
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" .vgpr_count: 0x1\n"
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" .registers:\n"
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" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
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" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
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"...\n";
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MCContext &MCCtx = MF->getContext();
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auto CC = CallingConv::AMDGPU_VS;
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MD.setFromString(yaml);
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MCSymbol *Sym = MCCtx.getOrCreateSymbol("Unknown");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(Sym, MCCtx), MCCtx);
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MD.setRsrc2(CC, MCConstantExpr::create(0xff00, MCCtx), MCCtx);
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std::string Output;
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MD.toString(Output);
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EXPECT_FALSE(MD.resolvedAllMCExpr());
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}
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TEST_F(PALMetadata, ResourceRegisterSetNoEmitUnresolved) {
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StringRef yaml = "---\n"
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"amdpal.pipelines:\n"
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" - .hardware_stages:\n"
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" .es:\n"
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" .entry_point: Test\n"
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" .scratch_memory_size: 0\n"
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" .sgpr_count: 0x1\n"
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" .vgpr_count: 0x1\n"
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" .registers:\n"
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" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
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" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
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"...\n";
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MCContext &MCCtx = MF->getContext();
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auto CC = CallingConv::AMDGPU_VS;
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MD.setFromString(yaml);
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MCSymbol *Sym = MCCtx.getOrCreateSymbol("Unknown");
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MD.setRsrc2(CC, MCSymbolRefExpr::create(Sym, MCCtx), MCCtx);
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MD.setRsrc2(CC, MCConstantExpr::create(0xff00, MCCtx), MCCtx);
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EXPECT_FALSE(MD.resolvedAllMCExpr());
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}
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