Florian Hahn 18ec3304a9 [VPlan] Manage InBounds via VPRecipeWithIRFlags for VectorPtrRecipe. ...

As suggested as follow-up in
https://github.com/llvm/llvm-project/pull/72164, manage inbounds via
VPRecipeWithIRFlags.

Note that in some cases we can now preserve inbounds in a few more
cases.

2024-01-07 13:58:05 +00:00

..

AArch64

[VPlan] Manage InBounds via VPRecipeWithIRFlags for VectorPtrRecipe.

2024-01-07 13:58:05 +00:00

ARM

Revert "[PM] Execute IndVarSimplifyPass precede RessociatePass" (#71617)

2023-11-08 09:22:55 +08:00

SystemZ

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X86

[VPlan] Model address separately. (#72164)

2024-01-01 19:51:15 +00:00

2010-03-22-empty-baseclass.ll

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assume-explosion.ll

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basic.ll

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bitcast-store-branch.ll

[FuncAttrs] Deduce noundef attributes for return values (#76553)

2023-12-31 20:44:48 +08:00

bitfield-bittests.ll

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cmp-logic.ll

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d83507-knowledge-retention-bug.ll

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dae-dce.ll

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dce-after-argument-promotion-loads.ll

[FuncAttrs] Deduce noundef attributes for return values (#76553)

2023-12-31 20:44:48 +08:00

dce-after-argument-promotion.ll

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deletion-of-loops-that-became-side-effect-free.ll

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dse-ephemeral-value-captures.ll

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early-arg-attrs-inference.ll

[FuncAttrs] Deduce noundef attributes for return values (#76553)

2023-12-31 20:44:48 +08:00

expect.ll

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fast-basictest.ll

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fast-reassociate-gvn.ll

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func-attrs.ll

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gdce.ll

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gep-null-compare-in-loop.ll

[FuncAttrs] Deduce noundef attributes for return values (#76553)

2023-12-31 20:44:48 +08:00

globalaa-retained.ll

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gvn-replacement-vs-hoist.ll

[InstCombine] Infer nneg on zext when forming from non-negative sext (#70706)

2023-10-30 12:09:43 -07:00

icmp-ashr-breaking-select-idiom.ll

Revert "Revert "[InstCombine] Add oneuse checks to shr + cmp constant folds.""

2023-10-28 03:12:15 -07:00

inlining-alignment-assumptions.ll

[InferAlignment] Enable InferAlignment pass by default

2023-09-20 12:08:52 +05:30

instcombine-sroa-inttoptr.ll

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lifetime-sanitizer.ll

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loop-access-checks.ll

[ConstraintElim] Use isKnownNonNegative for condition transfer. (#72879)

2023-11-21 10:09:35 +00:00

loop-rotation-vs-common-code-hoisting.ll

[ValueTracking] Add dominating condition support in computeKnownBits() (#73662)

2023-12-06 14:17:18 +01:00

lower-table-based-cttz.ll

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lto-licm.ll

[InstCombine] Infer nneg on zext when forming from non-negative sext (#70706)

2023-10-30 12:09:43 -07:00

memset-tail.ll

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min_max_loop.ll

[InstCombine] Use zext's nneg flag for icmp folding (#70845)

2023-11-13 00:53:53 +08:00

min-max-abs-cse.ll

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minmax.ll

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openmp-opt-module.ll

[OpenMP][NFC] Split the reduction buffer size into two components

2023-11-06 11:50:41 -08:00

partialord-ule.ll

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pr32544.ll

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pr36760.ll

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pr39116.ll

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pr39282.ll

[PhaseOrdering] Regenerate test checks (NFC)

2023-10-12 14:40:13 +02:00

pr40750.ll

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pr44461-br-to-switch-rotate.ll

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pr45682.ll

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pr45687.ll

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pr62311.ll

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pr64289-tce.ll

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PR6627.ll

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reassociate-after-unroll.ll

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reassociate-gvn-bdce.ll

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reassociate-instcombine.ll

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recompute-globalsaa.ll

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rotate.ll

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runtime-check-removal.ll

[ConstraintElim] Add (UGE, var, 0) to unsigned system for new vars. (#76262)

2023-12-23 15:53:48 +01:00

scev-custom-dl.ll

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scev.ll

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simplifycfg-options.ll

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simplifycfg-switch-lowering-vs-correlatedpropagation.ll

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single-iteration-loop-sroa.ll

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srem.ll

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swap-promotion.ll

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switch_with_geps.ll

[PhaseOrdering] Add data layout to test (NFC)

2023-12-20 11:49:34 +01:00

switch-sext.ll

[InstCombine] Fold switch(zext/sext(X)) into switch(X) (#76988)

2024-01-06 04:30:07 +08:00

two-shifts-by-sext.ll

[InstCombine] Add exact flags for ext idiom shr (shl X, Y), Y (#72483)

2023-11-16 17:30:01 +08:00

vector-select.ll

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vector-trunc-inseltpoison.ll

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vector-trunc.ll

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