4ae7e81233
This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
54 lines
1.7 KiB
LLVM
54 lines
1.7 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
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; Check the latency for instructions for both generic and cortex-a57.
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; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: foo:BB#0 entry
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; GENERIC: SDIV
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; GENERIC: Latency : 1
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; GENERIC: EORrr
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; GENERIC: Latency : 1
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; GENERIC: LDRi12
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; GENERIC: Latency : 4
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; GENERIC: ADDrr
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; GENERIC: Latency : 1
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; GENERIC: SUBrr
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; GENERIC: Latency : 1
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; A57_SCHED: SDIV
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; A57_SCHED: Latency : 20
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; A57_SCHED: EORrr
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; A57_SCHED: Latency : 1
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; A57_SCHED: LDRi12
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; A57_SCHED: Latency : 4
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; A57_SCHED: ADDrr
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; A57_SCHED: Latency : 1
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; A57_SCHED: SUBrr
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; A57_SCHED: Latency : 1
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; CHECK: ** Final schedule for BB#0 ***
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; GENERIC: LDRi12
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; GENERIC: SDIV
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; A57_SCHED: SDIV
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; A57_SCHED: LDRi12
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; CHECK: ********** INTERVALS **********
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8r-arm-none-eabi"
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; Function Attrs: norecurse nounwind readnone
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define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr #0 {
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entry:
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%xor = xor i32 %c, %b
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%ld = load i32, i32* %d
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%add = add nsw i32 %xor, %ld
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%div = sdiv i32 %a, %b
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%sub = sub i32 %div, %add
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ret i32 %sub
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}
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