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clang-p2996/llvm/lib/Target/RISCV
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4vtomat b3b2a9209b [RISCV] Fix the predicate code of uimm6 
Differential Revision: https://reviews.llvm.org/D156974
2023-08-03 03:42:14 -07:00
..
AsmParser
[RISCV] Remove zvk uimm constraints
2023-07-25 03:44:28 -07:00
Disassembler
[RISCV] Rename XTHead DecoderNamespaces to match their extension names include the 'X'. NFC
2023-07-30 12:09:03 -07:00
GISel
[RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
2023-07-14 18:22:53 -07:00
MCA
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
MCTargetDesc
[RISCV][MC][MSan] Fix uninitialized data members
2023-07-28 17:08:14 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.h
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.td
…
RISCVAsmPrinter.cpp
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV][NFC] Get rid of additional unneeded static_cast around RISCVSubtarget
2023-07-20 14:37:58 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV][NFC] Add RISCVSubtarget field to RISCVExpandPseudo and RISCVPreRAExpandPseudo
2023-07-21 16:50:11 +01:00
RISCVFeatures.td
[RISCV] Add support for XCVbi extension in CV32E40P
2023-07-28 21:54:10 +08:00
RISCVFrameLowering.cpp
[RISCV] Use max pushed register to get pushed register number.
2023-08-03 14:49:15 +08:00
RISCVFrameLowering.h
…
RISCVGatherScatterLowering.cpp
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
RISCVInstrFormats.td
[RISCV] Add a common base class for RVInstR variations. NFC
2023-07-31 13:06:23 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrInfo.cpp
[RISCV] Implement support for bf16 select when zfbfmin is enabled
2023-08-02 20:04:30 +01:00
RISCVInstrInfo.h
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVInstrInfo.td
[RISCV] Fix the predicate code of uimm6
2023-08-03 03:42:14 -07:00
RISCVInstrInfoA.td
[RISCV][MC] MC layer support for the experimental zacas extension
2023-07-10 08:26:31 +01:00
RISCVInstrInfoC.td
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
RISCVInstrInfoD.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoF.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoM.td
[NFC][RISCV] Rewrite TableGen files using named arguments
2023-07-20 17:17:49 +08:00
RISCVInstrInfoV.td
[RISCV] Add codegen support for bf16 vector
2023-07-28 09:54:23 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add codegen support for bf16 vector
2023-07-28 09:54:23 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Rename RISCVISD::FMINNUM_VL/FMAXNUM_VL to VFMIN_VL/VFMAX_VL. NFC
2023-08-02 11:53:06 -07:00
RISCVInstrInfoXCV.td
[RISCV] Add a common base class for RVInstR variations. NFC
2023-07-31 13:06:23 -07:00
RISCVInstrInfoXSf.td
[RISCV] Rename timm5 to tsimm5 to better reflect that it is a signed immediate.
2023-07-27 12:28:36 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Add a common base class for RVInstR variations. NFC
2023-07-31 13:06:23 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZb.td
[RISCV] Fix typo in C9LeftShift
2023-07-31 16:49:47 +08:00
RISCVInstrInfoZc.td
[RISCV] Add EmitPriority=0 to Zcb load/store aliases with no immediate offset.
2023-07-27 09:05:50 -07:00
RISCVInstrInfoZfa.td
[RISCV] Simplify tablegen class for Zfa FLI instructions. NFC
2023-07-25 09:33:54 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add codegen for Zfbfmin instructions
2023-07-24 10:37:58 +08:00
RISCVInstrInfoZfh.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Add support for llvm.prefetch to use Zicbop instructions.
2023-06-13 09:51:30 -07:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZk.td
[RISCV] Add a common base class for RVInstI variations. NFC
2023-07-31 13:03:35 -07:00
RISCVInstrInfoZvfbf.td
[RISCV][MC] Fix encoding for vfwmaccbf16
2023-06-23 14:01:52 +01:00
RISCVInstrInfoZvk.td
[RISCV] Add VP patterns for vwsll.[vv,vx,vi]
2023-08-03 00:43:13 +01:00
RISCVISelDAGToDAG.cpp
[RISCV] Copy memoperands in some of the post isel peepholes.
2023-08-02 09:16:14 -07:00
RISCVISelDAGToDAG.h
[RISCV] Copy memoperands in some of the post isel peepholes.
2023-08-02 09:16:14 -07:00
RISCVISelLowering.cpp
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
RISCVISelLowering.h
[RISCV] Rename RISCVISD::FMINNUM_VL/FMAXNUM_VL to VFMIN_VL/VFMAX_VL. NFC
2023-08-02 11:53:06 -07:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Fix incorrect return type of isPushable() to bool. NFC.
2023-07-26 17:04:47 +08:00
RISCVMacroFusion.cpp
…
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMergeBaseOffset.cpp
[RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.
2023-07-11 09:53:56 -07:00
RISCVMoveMerger.cpp
[RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style
2023-06-27 13:35:41 +01:00
RISCVOptWInstrs.cpp
…
RISCVProcessors.td
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
RISCVPushPopOptimizer.cpp
[RISCV][NFC] Get rid of additional unneeded static_cast around RISCVSubtarget
2023-07-20 14:37:58 +01:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Don't include X1 in the X0_PD register pair
2023-07-20 13:48:15 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Add codegen support for bf16 vector
2023-07-28 09:54:23 +08:00
RISCVRVVInitUndef.cpp
[RISCVRVVInitUndef] Ignore tied use for partial undef register
2023-08-01 12:16:26 -07:00
RISCVSchedRocket.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVSchedSiFive7.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVSchedule.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVScheduleV.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2023-06-02 23:14:17 -07:00
RISCVSubtarget.h
[RISCV] Simplify some predicate functions in RISCVSubtarget.h. NFC
2023-07-30 12:37:50 -07:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][CostModel] Model vrgather.vv as being quadradic in LMUL
2023-07-18 11:52:34 -07:00
RISCVTargetTransformInfo.h
[LV] Rename the Select[I|F]Cmp reduction pattern to [I|F]AnyOf. (NFC)
2023-08-03 00:37:19 -07:00