5b95bba6fe
The +unaligned-scalar-mem and +unaligned-vector-mem features were added in D126085 and D149375 respectively to allow subtargets to indicate that they supported misaligned loads/stores with "sufficient" performance. This is separate from whether or not the target actually supports misaligned accesses, which could be determined from Zicclsm. This patch enables the Fast flag under the assumption that any subtarget that declares support for +unaligned-*-mem will want to opt into optimisations that take advantage of misaligned scalar accesses, such as store merging. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D150771
418 lines
11 KiB
LLVM
418 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,SLOW,RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,SLOW,RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,FAST,RV32I-FAST %s
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; RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,FAST,RV64I-FAST %s
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; A collection of cases showing codegen for unaligned loads and stores
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define i8 @load_i8(ptr %p) {
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; ALL-LABEL: load_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: lbu a0, 0(a0)
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; ALL-NEXT: ret
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%res = load i8, ptr %p, align 1
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ret i8 %res
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}
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define i16 @load_i16(ptr %p) {
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; SLOW-LABEL: load_i16:
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; SLOW: # %bb.0:
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; SLOW-NEXT: lbu a1, 1(a0)
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; SLOW-NEXT: lbu a0, 0(a0)
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; SLOW-NEXT: slli a1, a1, 8
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; SLOW-NEXT: or a0, a1, a0
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: load_i16:
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; FAST: # %bb.0:
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; FAST-NEXT: lh a0, 0(a0)
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; FAST-NEXT: ret
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%res = load i16, ptr %p, align 1
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ret i16 %res
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}
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define i24 @load_i24(ptr %p) {
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; SLOW-LABEL: load_i24:
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; SLOW: # %bb.0:
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; SLOW-NEXT: lbu a1, 1(a0)
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; SLOW-NEXT: lbu a2, 0(a0)
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; SLOW-NEXT: lbu a0, 2(a0)
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; SLOW-NEXT: slli a1, a1, 8
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; SLOW-NEXT: or a1, a1, a2
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; SLOW-NEXT: slli a0, a0, 16
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; SLOW-NEXT: or a0, a1, a0
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: load_i24:
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; FAST: # %bb.0:
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; FAST-NEXT: lbu a1, 2(a0)
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; FAST-NEXT: lhu a0, 0(a0)
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; FAST-NEXT: slli a1, a1, 16
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; FAST-NEXT: or a0, a0, a1
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; FAST-NEXT: ret
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%res = load i24, ptr %p, align 1
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ret i24 %res
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}
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define i32 @load_i32(ptr %p) {
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; SLOW-LABEL: load_i32:
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; SLOW: # %bb.0:
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; SLOW-NEXT: lbu a1, 1(a0)
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; SLOW-NEXT: lbu a2, 0(a0)
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; SLOW-NEXT: lbu a3, 2(a0)
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; SLOW-NEXT: lbu a0, 3(a0)
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; SLOW-NEXT: slli a1, a1, 8
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; SLOW-NEXT: or a1, a1, a2
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; SLOW-NEXT: slli a3, a3, 16
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; SLOW-NEXT: slli a0, a0, 24
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; SLOW-NEXT: or a0, a0, a3
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; SLOW-NEXT: or a0, a0, a1
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: load_i32:
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; FAST: # %bb.0:
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; FAST-NEXT: lw a0, 0(a0)
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; FAST-NEXT: ret
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%res = load i32, ptr %p, align 1
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ret i32 %res
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}
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define i64 @load_i64(ptr %p) {
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; RV32I-LABEL: load_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a2, 0(a0)
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; RV32I-NEXT: lbu a3, 2(a0)
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; RV32I-NEXT: lbu a4, 3(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: slli a3, a3, 16
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; RV32I-NEXT: slli a4, a4, 24
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; RV32I-NEXT: or a2, a4, a3
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; RV32I-NEXT: or a2, a2, a1
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; RV32I-NEXT: lbu a1, 5(a0)
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; RV32I-NEXT: lbu a3, 4(a0)
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; RV32I-NEXT: lbu a4, 6(a0)
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; RV32I-NEXT: lbu a0, 7(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: slli a4, a4, 16
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: or a0, a0, a4
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; RV32I-NEXT: or a1, a0, a1
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a2, 0(a0)
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; RV64I-NEXT: lbu a3, 2(a0)
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; RV64I-NEXT: lbu a4, 3(a0)
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a3, a3, 16
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; RV64I-NEXT: slli a4, a4, 24
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; RV64I-NEXT: or a3, a4, a3
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; RV64I-NEXT: or a1, a3, a1
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; RV64I-NEXT: lbu a2, 5(a0)
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; RV64I-NEXT: lbu a3, 4(a0)
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; RV64I-NEXT: lbu a4, 6(a0)
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; RV64I-NEXT: lbu a0, 7(a0)
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; RV64I-NEXT: slli a2, a2, 8
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; RV64I-NEXT: or a2, a2, a3
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; RV64I-NEXT: slli a4, a4, 16
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; RV64I-NEXT: slli a0, a0, 24
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; RV64I-NEXT: or a0, a0, a4
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-FAST-LABEL: load_i64:
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; RV32I-FAST: # %bb.0:
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; RV32I-FAST-NEXT: lw a2, 0(a0)
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; RV32I-FAST-NEXT: lw a1, 4(a0)
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; RV32I-FAST-NEXT: mv a0, a2
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; RV32I-FAST-NEXT: ret
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;
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; RV64I-FAST-LABEL: load_i64:
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; RV64I-FAST: # %bb.0:
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; RV64I-FAST-NEXT: ld a0, 0(a0)
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; RV64I-FAST-NEXT: ret
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%res = load i64, ptr %p, align 1
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ret i64 %res
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}
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define void @store_i8(ptr %p, i8 %v) {
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; ALL-LABEL: store_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: sb a1, 0(a0)
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; ALL-NEXT: ret
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store i8 %v, ptr %p, align 1
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ret void
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}
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define void @store_i16(ptr %p, i16 %v) {
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; SLOW-LABEL: store_i16:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sb a1, 0(a0)
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; SLOW-NEXT: srli a1, a1, 8
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; SLOW-NEXT: sb a1, 1(a0)
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: store_i16:
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; FAST: # %bb.0:
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; FAST-NEXT: sh a1, 0(a0)
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; FAST-NEXT: ret
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store i16 %v, ptr %p, align 1
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ret void
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}
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define void @store_i24(ptr %p, i24 %v) {
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; SLOW-LABEL: store_i24:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sb a1, 0(a0)
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; SLOW-NEXT: srli a2, a1, 8
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; SLOW-NEXT: sb a2, 1(a0)
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; SLOW-NEXT: srli a1, a1, 16
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; SLOW-NEXT: sb a1, 2(a0)
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: store_i24:
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; FAST: # %bb.0:
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; FAST-NEXT: sh a1, 0(a0)
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; FAST-NEXT: srli a1, a1, 16
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; FAST-NEXT: sb a1, 2(a0)
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; FAST-NEXT: ret
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store i24 %v, ptr %p, align 1
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ret void
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}
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define void @store_i32(ptr %p, i32 %v) {
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; SLOW-LABEL: store_i32:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sb a1, 0(a0)
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; SLOW-NEXT: srli a2, a1, 24
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; SLOW-NEXT: sb a2, 3(a0)
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; SLOW-NEXT: srli a2, a1, 16
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; SLOW-NEXT: sb a2, 2(a0)
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; SLOW-NEXT: srli a1, a1, 8
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; SLOW-NEXT: sb a1, 1(a0)
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: store_i32:
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; FAST: # %bb.0:
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; FAST-NEXT: sw a1, 0(a0)
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; FAST-NEXT: ret
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store i32 %v, ptr %p, align 1
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ret void
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}
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define void @store_i64(ptr %p, i64 %v) {
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; RV32I-LABEL: store_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sb a2, 4(a0)
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: srli a3, a2, 24
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; RV32I-NEXT: sb a3, 7(a0)
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; RV32I-NEXT: srli a3, a2, 16
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; RV32I-NEXT: sb a3, 6(a0)
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; RV32I-NEXT: srli a2, a2, 8
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; RV32I-NEXT: sb a2, 5(a0)
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; RV32I-NEXT: srli a2, a1, 24
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; RV32I-NEXT: sb a2, 3(a0)
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; RV32I-NEXT: srli a2, a1, 16
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; RV32I-NEXT: sb a2, 2(a0)
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; RV32I-NEXT: srli a1, a1, 8
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; RV32I-NEXT: sb a1, 1(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: store_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sb a1, 0(a0)
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; RV64I-NEXT: srli a2, a1, 56
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; RV64I-NEXT: sb a2, 7(a0)
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; RV64I-NEXT: srli a2, a1, 48
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; RV64I-NEXT: sb a2, 6(a0)
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; RV64I-NEXT: srli a2, a1, 40
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; RV64I-NEXT: sb a2, 5(a0)
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; RV64I-NEXT: srli a2, a1, 32
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; RV64I-NEXT: sb a2, 4(a0)
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; RV64I-NEXT: srli a2, a1, 24
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; RV64I-NEXT: sb a2, 3(a0)
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; RV64I-NEXT: srli a2, a1, 16
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; RV64I-NEXT: sb a2, 2(a0)
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; RV64I-NEXT: srli a1, a1, 8
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; RV64I-NEXT: sb a1, 1(a0)
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; RV64I-NEXT: ret
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;
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; RV32I-FAST-LABEL: store_i64:
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; RV32I-FAST: # %bb.0:
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; RV32I-FAST-NEXT: sw a2, 4(a0)
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; RV32I-FAST-NEXT: sw a1, 0(a0)
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; RV32I-FAST-NEXT: ret
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;
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; RV64I-FAST-LABEL: store_i64:
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; RV64I-FAST: # %bb.0:
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; RV64I-FAST-NEXT: sd a1, 0(a0)
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; RV64I-FAST-NEXT: ret
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store i64 %v, ptr %p, align 1
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ret void
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}
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define void @merge_stores_i8_i16(ptr %p) {
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; SLOW-LABEL: merge_stores_i8_i16:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sb zero, 0(a0)
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; SLOW-NEXT: sb zero, 1(a0)
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: merge_stores_i8_i16:
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; FAST: # %bb.0:
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; FAST-NEXT: sh zero, 0(a0)
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; FAST-NEXT: ret
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store i8 0, ptr %p
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%p2 = getelementptr i8, ptr %p, i32 1
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store i8 0, ptr %p2
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ret void
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}
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define void @merge_stores_i8_i32(ptr %p) {
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; SLOW-LABEL: merge_stores_i8_i32:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sb zero, 0(a0)
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; SLOW-NEXT: sb zero, 1(a0)
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; SLOW-NEXT: sb zero, 2(a0)
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; SLOW-NEXT: sb zero, 3(a0)
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: merge_stores_i8_i32:
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; FAST: # %bb.0:
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; FAST-NEXT: sw zero, 0(a0)
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; FAST-NEXT: ret
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store i8 0, ptr %p
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%p2 = getelementptr i8, ptr %p, i32 1
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store i8 0, ptr %p2
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%p3 = getelementptr i8, ptr %p, i32 2
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store i8 0, ptr %p3
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%p4 = getelementptr i8, ptr %p, i32 3
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store i8 0, ptr %p4
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ret void
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}
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define void @merge_stores_i8_i64(ptr %p) {
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; SLOW-LABEL: merge_stores_i8_i64:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sb zero, 0(a0)
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; SLOW-NEXT: sb zero, 1(a0)
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; SLOW-NEXT: sb zero, 2(a0)
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; SLOW-NEXT: sb zero, 3(a0)
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; SLOW-NEXT: sb zero, 4(a0)
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; SLOW-NEXT: sb zero, 5(a0)
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; SLOW-NEXT: sb zero, 6(a0)
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; SLOW-NEXT: sb zero, 7(a0)
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; SLOW-NEXT: ret
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;
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; RV32I-FAST-LABEL: merge_stores_i8_i64:
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; RV32I-FAST: # %bb.0:
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; RV32I-FAST-NEXT: sw zero, 0(a0)
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; RV32I-FAST-NEXT: sw zero, 4(a0)
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; RV32I-FAST-NEXT: ret
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;
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; RV64I-FAST-LABEL: merge_stores_i8_i64:
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; RV64I-FAST: # %bb.0:
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; RV64I-FAST-NEXT: sd zero, 0(a0)
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; RV64I-FAST-NEXT: ret
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store i8 0, ptr %p
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%p2 = getelementptr i8, ptr %p, i32 1
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store i8 0, ptr %p2
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%p3 = getelementptr i8, ptr %p, i32 2
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store i8 0, ptr %p3
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%p4 = getelementptr i8, ptr %p, i32 3
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store i8 0, ptr %p4
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%p5 = getelementptr i8, ptr %p, i32 4
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store i8 0, ptr %p5
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%p6 = getelementptr i8, ptr %p, i32 5
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store i8 0, ptr %p6
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%p7 = getelementptr i8, ptr %p, i32 6
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store i8 0, ptr %p7
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%p8 = getelementptr i8, ptr %p, i32 7
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store i8 0, ptr %p8
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ret void
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}
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define void @merge_stores_i16_i32(ptr %p) {
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; SLOW-LABEL: merge_stores_i16_i32:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sh zero, 0(a0)
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; SLOW-NEXT: sh zero, 2(a0)
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; SLOW-NEXT: ret
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;
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; FAST-LABEL: merge_stores_i16_i32:
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; FAST: # %bb.0:
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; FAST-NEXT: sw zero, 0(a0)
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; FAST-NEXT: ret
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store i16 0, ptr %p
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%p2 = getelementptr i16, ptr %p, i32 1
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store i16 0, ptr %p2
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ret void
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}
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define void @merge_stores_i16_i64(ptr %p) {
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; SLOW-LABEL: merge_stores_i16_i64:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sh zero, 0(a0)
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; SLOW-NEXT: sh zero, 2(a0)
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; SLOW-NEXT: sh zero, 4(a0)
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; SLOW-NEXT: sh zero, 6(a0)
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; SLOW-NEXT: ret
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;
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; RV32I-FAST-LABEL: merge_stores_i16_i64:
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; RV32I-FAST: # %bb.0:
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; RV32I-FAST-NEXT: sw zero, 0(a0)
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; RV32I-FAST-NEXT: sw zero, 4(a0)
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; RV32I-FAST-NEXT: ret
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;
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; RV64I-FAST-LABEL: merge_stores_i16_i64:
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; RV64I-FAST: # %bb.0:
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; RV64I-FAST-NEXT: sd zero, 0(a0)
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; RV64I-FAST-NEXT: ret
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store i16 0, ptr %p
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%p2 = getelementptr i16, ptr %p, i32 1
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store i16 0, ptr %p2
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%p3 = getelementptr i16, ptr %p, i32 2
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store i16 0, ptr %p3
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%p4 = getelementptr i16, ptr %p, i32 3
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store i16 0, ptr %p4
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ret void
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}
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define void @merge_stores_i32_i64(ptr %p) {
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; SLOW-LABEL: merge_stores_i32_i64:
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; SLOW: # %bb.0:
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; SLOW-NEXT: sw zero, 0(a0)
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; SLOW-NEXT: sw zero, 4(a0)
|
|
; SLOW-NEXT: ret
|
|
;
|
|
; RV32I-FAST-LABEL: merge_stores_i32_i64:
|
|
; RV32I-FAST: # %bb.0:
|
|
; RV32I-FAST-NEXT: sw zero, 0(a0)
|
|
; RV32I-FAST-NEXT: sw zero, 4(a0)
|
|
; RV32I-FAST-NEXT: ret
|
|
;
|
|
; RV64I-FAST-LABEL: merge_stores_i32_i64:
|
|
; RV64I-FAST: # %bb.0:
|
|
; RV64I-FAST-NEXT: sd zero, 0(a0)
|
|
; RV64I-FAST-NEXT: ret
|
|
store i32 0, ptr %p
|
|
%p2 = getelementptr i32, ptr %p, i32 1
|
|
store i32 0, ptr %p2
|
|
ret void
|
|
}
|