Thomas Symalla f2ef2fbc69 Renamed identifiers in lit

2021-02-02 09:14:53 +01:00

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AArch64

Revert "[AArch64] Homogeneous Prolog and Epilog Size Optimization"

2021-02-02 02:33:44 -05:00

AMDGPU

Renamed identifiers in lit

2021-02-02 09:14:53 +01:00

ARC

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ARM

[ARM] Simplify VMOVRRD from extracts of buildvectors

2021-02-01 16:09:25 +00:00

AVR

[AVR] Optimize 16-bit int shift

2021-01-28 15:10:11 +08:00

BPF

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Generic

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Hexagon

[NewPM][opt] Run the "default" AA pipeline by default

2021-01-21 21:08:54 -08:00

Inputs

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Lanai

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Mips

[CodeGen] Try to make the print of memory operand alignment a little more user friendly.

2021-01-11 19:58:47 -08:00

MIR

[AMDGPU] Implement mir parseCustomPseudoSourceValue

2021-01-22 11:24:08 +01:00

MSP430

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NVPTX

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PowerPC

[PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases

2021-01-28 15:17:32 -05:00

RISCV

[RISCV] Add scalable vector support for floating point FMA instructions

2021-02-01 09:52:43 -08:00

SPARC

[SPARC] Fix fp128 load/stores

2021-01-13 14:59:50 -08:00

SystemZ

[SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds

2021-01-14 15:46:27 +00:00

Thumb

[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer

2021-01-23 09:10:03 +00:00

Thumb2

[ARM] Flatten identity shuffles through vqdmulh nodes

2021-02-01 19:14:20 +00:00

VE

[VE] Update VELIntrinsic tests

2021-01-13 00:12:50 +09:00

WebAssembly

[WebAssembly] Prototype i8x16 to i32x4 widening instructions

2021-01-28 10:59:32 -08:00

WinCFGuard

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WinEH

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X86

[x86] introduce no_callee_saved_registers attribute

2021-02-01 16:19:14 -08:00

XCore

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