ebbc5de7db
The m68k backend will always emit external calls (including libcalls) with PC-relative PLT relocations, even when in non-pic mode or -fno-plt is used. This is unexpected, as other function calls are emitted with absolute addressing, and a static code modes suggests that there is no PLT. It also leads to a miscompilation where the call instruction emitted expects an immediate address, while the relocation emitted for that instruction is PC-relative. This miscompilation can even be seen in the default C function in godbolt: https://godbolt.org/z/zEoazovzo Fix the issue by classifying external function references based upon the pic mode. This triggers a change in the static code model, making it more in line with the expected behaviour and allowing use of this backend in more bare-metal situations where a PLT does not exist. The change avoids the issue where we emit a PLT32 relocation for an absolute call, and makes libcalls and other external calls use absolute addressing modes when a static code model is desired. Further work should be done in instruction lowering and validation to ensure that miscompilations of the same type don't occur.
181 lines
4.2 KiB
LLVM
181 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=m68k -verify-machineinstrs \
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; RUN: -code-model=medium -relocation-model=static \
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; RUN: | FileCheck %s
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@ptr = external global ptr
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@dst = external global i32
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@src = external global i32
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define void @test0() nounwind {
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; CHECK-LABEL: test0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l #dst, ptr
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; CHECK-NEXT: move.l src, dst
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; CHECK-NEXT: rts
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entry:
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store ptr @dst, ptr @ptr
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%tmp.s = load i32, ptr @src
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store i32 %tmp.s, ptr @dst
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ret void
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}
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@ptr2 = global ptr null
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@dst2 = global i32 0
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@src2 = global i32 0
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define void @test1() nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l #dst2, ptr2
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; CHECK-NEXT: move.l src2, dst2
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; CHECK-NEXT: rts
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entry:
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store ptr @dst2, ptr @ptr2
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%tmp.s = load i32, ptr @src2
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store i32 %tmp.s, ptr @dst2
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ret void
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}
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declare ptr @malloc(i32)
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define void @test2() nounwind {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: move.l #40, (%sp)
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; CHECK-NEXT: jsr malloc
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%ptr = call ptr @malloc(i32 40)
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ret void
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}
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@pfoo = external global ptr
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declare ptr @afoo(...)
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define void @test3() nounwind {
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; CHECK-LABEL: test3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: jsr afoo
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; CHECK-NEXT: move.l %a0, pfoo
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; CHECK-NEXT: jsr (%a0)
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%tmp = call ptr(...) @afoo()
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store ptr %tmp, ptr @pfoo
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%tmp1 = load ptr, ptr @pfoo
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call void(...) %tmp1()
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ret void
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}
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declare void @foo(...)
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define void @test4() nounwind {
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; CHECK-LABEL: test4:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: jsr foo
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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call void(...) @foo()
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ret void
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}
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@ptr6 = internal global ptr null
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@dst6 = internal global i32 0
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@src6 = internal global i32 0
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define void @test5() nounwind {
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; CHECK-LABEL: test5:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l #dst6, ptr6
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; CHECK-NEXT: move.l src6, dst6
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; CHECK-NEXT: rts
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entry:
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store ptr @dst6, ptr @ptr6
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%tmp.s = load i32, ptr @src6
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store i32 %tmp.s, ptr @dst6
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ret void
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}
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define void @test7(i32 %n.u) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: add.l #-1, %d0
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: sub.l #12, %d1
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; CHECK-NEXT: bhi .LBB6_12
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: lsl.l #2, %d0
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; CHECK-NEXT: move.l #.LJTI6_0, %a0
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; CHECK-NEXT: move.l (0,%a0,%d0), %a0
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; CHECK-NEXT: jmp (%a0)
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; CHECK-NEXT: .LBB6_12: ; %bb2
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; CHECK-NEXT: bra foo6 ; TAILCALL
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; CHECK-NEXT: .LBB6_3: ; %bb5
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; CHECK-NEXT: bra foo5 ; TAILCALL
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; CHECK-NEXT: .LBB6_5: ; %bb1
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; CHECK-NEXT: bra foo2 ; TAILCALL
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; CHECK-NEXT: .LBB6_2: ; %bb
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; CHECK-NEXT: bra foo1 ; TAILCALL
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; CHECK-NEXT: .LBB6_9: ; %bb4
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; CHECK-NEXT: bra foo4 ; TAILCALL
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; CHECK-NEXT: .LBB6_8: ; %bb3
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; CHECK-NEXT: bra foo3 ; TAILCALL
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entry:
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switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
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bb:
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tail call void(...) @foo1()
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ret void
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bb1:
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tail call void(...) @foo2()
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ret void
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bb2:
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tail call void(...) @foo6()
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ret void
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bb3:
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tail call void(...) @foo3()
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ret void
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bb4:
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tail call void(...) @foo4()
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ret void
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bb5:
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tail call void(...) @foo5()
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ret void
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bb6:
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tail call void(...) @foo1()
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ret void
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bb7:
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tail call void(...) @foo2()
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ret void
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bb8:
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tail call void(...) @foo6()
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ret void
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bb9:
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tail call void(...) @foo3()
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ret void
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bb10:
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tail call void(...) @foo4()
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ret void
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bb11:
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tail call void(...) @foo5()
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ret void
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bb12:
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tail call void(...) @foo6()
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ret void
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}
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declare void @foo1(...)
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declare void @foo2(...)
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declare void @foo6(...)
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declare void @foo3(...)
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declare void @foo4(...)
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declare void @foo5(...)
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