b14e83d1a4
We currently have log, log2, log10, exp and exp2 intrinsics. Add exp10 to fix this asymmetry. AMDGPU already has most of the code for f32 exp10 expansion implemented alongside exp, so the current implementation is duplicating nearly identical effort between the compiler and library which is inconvenient. https://reviews.llvm.org/D157871
64 lines
1.8 KiB
LLVM
64 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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define float @call_exp10f(float %a) {
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; CHECK-LABEL: call_exp10f:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: bl exp10f
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call float @exp10f(float %a)
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ret float %result
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}
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define double @call_exp10(double %a) {
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; CHECK-LABEL: call_exp10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: bl exp10
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call double @exp10(double %a)
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ret double %result
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}
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define ppc_fp128 @call_exp10l(ppc_fp128 %a) {
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; CHECK-LABEL: call_exp10l:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: bl exp10l
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call ppc_fp128 @exp10l(ppc_fp128 %a)
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ret ppc_fp128 %result
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}
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declare float @exp10f(float %a) #0
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declare double @exp10(double %a) #0
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declare ppc_fp128 @exp10l(ppc_fp128 %a) #0
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attributes #0 = { nounwind readonly }
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