Stanislav Mekhanoshin cb9ae93712 [AMDGPU] Define SGPR_NULL64 register. NFCI. ...

On gfx10+ null register can be used as both 32 and 64 bit operand.
Define a 64 bit version of the register to use during codegen.

Differential Revision: https://reviews.llvm.org/D127527

2022-06-13 13:23:33 -07:00

..

AMDGPUAsmUtils.cpp

[AMDGPU] gfx11 scalar alu instructions

2022-05-17 13:35:41 -04:00

AMDGPUAsmUtils.h

[AMDGPU] gfx11 BUF Instructions

2022-05-16 09:41:40 -04:00

AMDGPUBaseInfo.cpp

[AMDGPU] Define SGPR_NULL64 register. NFCI.

2022-06-13 13:23:33 -07:00

AMDGPUBaseInfo.h

[AMDGPU] gfx11 Image instructions

2022-05-31 10:53:35 -04:00

AMDGPUMemoryUtils.cpp

[AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

2022-05-11 13:22:51 -07:00

AMDGPUMemoryUtils.h

[AMDGPU][NFC] Fix typos

2022-02-18 15:05:21 +01:00

AMDGPUPALMetadata.cpp

[AMDGPU] Add agpr_count to metadata and AsmParser

2022-02-16 15:17:23 -08:00

AMDGPUPALMetadata.h

[AMDGPU] Add agpr_count to metadata and AsmParser

2022-02-16 15:17:23 -08:00

AMDKernelCodeTInfo.h

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AMDKernelCodeTUtils.cpp

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AMDKernelCodeTUtils.h

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CMakeLists.txt

[AMDGPU] Merge AMDGPULDSUtils into AMDGPUMemoryUtils

2022-02-11 10:32:24 -08:00