clang-p2996

AsmParser

[RISCV] Teach .option arch to support experimental extensions. (#89727 )

2024-05-06 13:55:37 +08:00

Disassembler

[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371 )

2024-04-29 10:11:28 -07:00

GISel

[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292 )

2024-05-02 10:32:40 +08:00

MCA

[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc

2024-04-24 09:29:20 -07:00

MCTargetDesc

[RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp. (#89014 )

2024-05-02 14:04:55 +08:00

TargetInfo

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CMakeLists.txt

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770 )

2024-02-26 12:12:31 +00:00

RISCV.h

Reapply "[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295 )"

2024-04-25 00:42:30 +08:00

RISCV.td

[RISCV] Add subtarget features for profiles

2024-04-28 11:32:37 +08:00

RISCVAsmPrinter.cpp

[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684 )

2024-04-23 15:12:36 -07:00

RISCVCallingConv.td

[RISCV] RISCV vector calling convention (1/2) (#77560 )

2024-03-27 23:03:13 +08:00

RISCVCodeGenPrepare.cpp

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RISCVCombine.td

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RISCVDeadRegisterDefinitions.cpp

[RISCV] Move RISCVDeadRegisterDefinitions to post vector regalloc (#90636 )

2024-05-07 00:36:47 +08:00

RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVFeatures.td

[RISCV] Add smstateen extension (#90818 )

2024-05-02 09:12:44 -07:00

RISCVFoldMasks.cpp

[RISCV] Use DenseMap to track V0 definition. NFC (#84465 )

2024-03-21 15:38:43 +08:00

RISCVFrameLowering.cpp

[RISCV] Add CFI information for vector callee-saved registers (#86811 )

2024-04-17 10:42:40 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811 )

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

[NFC][RemoveDIs] Use iterators for insertion at various call-sites (#84736 )

2024-03-19 16:36:29 +00:00

RISCVGISel.td

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RISCVInsertReadWriteCSR.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVInsertVSETVLI.cpp

[RISCV] Check dead flag on VL def op in RISCVCoalesceVSETVLI. NFC (#91168 )

2024-05-07 00:02:42 +08:00

RISCVInsertWriteVXRM.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVInstrFormats.td

[RISCV] Rename OP-P to OP-VE. (#87546 )

2024-04-05 17:02:03 -07:00

RISCVInstrFormatsC.td

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RISCVInstrFormatsV.td

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RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVInstrInfo.cpp

[RISCV] Make fixed-point instructions commutable (#90035 )

2024-04-28 12:04:09 +08:00

RISCVInstrInfo.h

[RISCV][MachineCombiner] Add reassociation optimizations for RVV instructions (#88307 )

2024-04-25 16:36:11 -07:00

RISCVInstrInfo.td

[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292 )

2024-05-02 10:32:40 +08:00

RISCVInstrInfoA.td

[RISCV] Remove mayLoad = 1 from store-conditional (#88470 )

2024-04-12 08:45:47 -07:00

RISCVInstrInfoC.td

[RISCV][NFC] Future-proof reference to ISA manual in RISCVInstrInfoC.td

2024-04-26 13:49:27 +01:00

RISCVInstrInfoD.td

[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887 )

2024-03-20 08:44:24 -07:00

RISCVInstrInfoF.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoM.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385 )

2024-03-07 14:03:58 -08:00

RISCVInstrInfoSFB.td

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RISCVInstrInfoV.td

[RISCV] Model vd as a src for some Zvk* instructions in MC layer. (#86710 )

2024-03-27 12:20:24 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Add codegen support for Zvfbfmin (#87911 )

2024-05-07 10:25:06 +08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Add codegen support for Zvfbfmin (#87911 )

2024-05-07 10:25:06 +08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Add codegen support for Zvfbfmin (#87911 )

2024-05-07 10:25:06 +08:00

RISCVInstrInfoXCV.td

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RISCVInstrInfoXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVInstrInfoXTHead.td

Reapply "[RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (#89263 )"

2024-04-23 08:30:38 -07:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoZa.td

[RISCV][ISel] Add codegen support for the experimental zabha extension (#80192 )

2024-02-16 15:35:09 +08:00

RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789 )

2024-04-23 12:40:55 -07:00

RISCVInstrInfoZc.td

[RISCV] Add validation of SPIMM for cm.push/pop. (#84989 )

2024-03-28 08:38:18 -07:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826 )

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

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RISCVInstrInfoZfbfmin.td

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RISCVInstrInfoZfh.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

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RISCVInstrInfoZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVISelDAGToDAG.cpp

[RISCV] Handle fixed length vectors with exact VLEN in lowerINSERT_SUBVECTOR (#84107 )

2024-05-01 01:35:13 +08:00

RISCVISelDAGToDAG.h

[RISCV][NFC] Move RISCVMaskedPseudoTable to RISCVInstrInfo

2024-04-24 09:29:20 -07:00

RISCVISelLowering.cpp

[RISCV] Add codegen support for Zvfbfmin (#87911 )

2024-05-07 10:25:06 +08:00

RISCVISelLowering.h

[VP][RISCV] Add vp.cttz.elts intrinsic and its RISC-V codegen (#90502 )

2024-04-30 09:27:10 -07:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

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RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375 )

2024-03-27 13:40:38 +08:00

RISCVMergeBaseOffset.cpp

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RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Remove extra indentation from RISCVProcessors.td.

2024-04-20 19:21:59 -07:00

RISCVProfiles.td

[RISCV] Add subtarget features for profiles

2024-04-28 11:32:37 +08:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174 )

2024-04-19 12:39:32 -07:00

RISCVRegisterInfo.h

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVRegisterInfo.td

[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292 )

2024-05-02 10:32:40 +08:00

RISCVSchedRocket.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedSiFive7.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedSiFiveP400.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedSiFiveP600.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedSyntacoreSCR1.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedule.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVScheduleV.td

[RISCV] Fix typo in RISCVScheduleV.td that was introduced in 60a1158

2024-04-17 10:16:02 -07:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVScheduleZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSubtarget.cpp

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RISCVSubtarget.h

[RISCV] Handle fixed length vectors with exact VLEN in lowerINSERT_SUBVECTOR (#84107 )

2024-05-01 01:35:13 +08:00

RISCVSystemOperands.td

[RISCV] Add the CSR names from Smrnmi. (#83370 )

2024-03-19 21:27:25 -07:00

RISCVTargetMachine.cpp

[RISCV] Move RISCVDeadRegisterDefinitions to post vector regalloc (#90636 )

2024-05-07 00:36:47 +08:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetObjectFile.h

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetTransformInfo.cpp

[RISCV] Support interleaved accesses for scalable vector. (#90583 )

2024-05-03 21:56:31 +08:00

RISCVTargetTransformInfo.h

[TTI] getArithmeticInstrCost - use std:nullopt to create default empty ArrayRef<const Value *> Args argument. NFC.

2024-04-24 10:51:18 +01:00