f768083516
This PR contains a series of fixes which are to improve type inference and instruction selection. Namely, it includes: * fix OpSelect to support operands of a pointer type, according to the SPIR-V specification (previously only integer/float/vectors of integer or float were supported) -- a new test case is added and existing test case is updated; * fix TableGen typo's in definition of register classes and introduce a new reg class that is a vector of pointers; * fix usage of a machine function context when there is a need to switch between different machine functions to infer/validate correct types; * add usage of TypedPointerType instead of PointerType so that later stages of type inference are able to distinguish pointer types by their element types, effectively supporting hierarchy of pointer/pointee types and avoiding more complicated recursive type matching on level of machine instructions in favor of direct pointer comparison using LLVM's `Type *` values; * extracting detailed information about operand types using known type rules for some llvm instructions (for instance, by deducing PHI's operand pointee types if PHI's results type was deducted on previous stages of type inference), and adding correspondent `Intrinsic::spv_assign_ptr_type` to keep type info along consequent passes, * ensure that OpConstantComposite reuses a constant when it's already created and available in the same machine function -- otherwise there is a crash while building a dependency graph, the corresponding test case is attached, * implement deduction of function's return type for opaque pointers, a new test case is attached, * make 'emit intrinsics' a module pass to resolve function return types over the module -- first types for all functions of the module must be calculated, and only after that it's feasible to deduct function return types on this earlier stage of translation.
624 lines
25 KiB
C++
624 lines
25 KiB
C++
//===--- SPIRVCallLowering.cpp - Call lowering ------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the lowering of LLVM calls to machine code calls for
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// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVCallLowering.h"
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#include "MCTargetDesc/SPIRVBaseInfo.h"
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#include "SPIRV.h"
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#include "SPIRVBuiltins.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVISelLowering.h"
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#include "SPIRVMetadata.h"
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#include "SPIRVRegisterInfo.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVUtils.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#include "llvm/Support/ModRef.h"
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using namespace llvm;
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SPIRVCallLowering::SPIRVCallLowering(const SPIRVTargetLowering &TLI,
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SPIRVGlobalRegistry *GR)
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: CallLowering(&TLI), GR(GR) {}
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bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI,
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Register SwiftErrorVReg) const {
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// Maybe run postponed production of types for function pointers
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if (IndirectCalls.size() > 0) {
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produceIndirectPtrTypes(MIRBuilder);
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IndirectCalls.clear();
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}
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// Currently all return types should use a single register.
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// TODO: handle the case of multiple registers.
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if (VRegs.size() > 1)
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return false;
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if (Val) {
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const auto &STI = MIRBuilder.getMF().getSubtarget();
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return MIRBuilder.buildInstr(SPIRV::OpReturnValue)
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.addUse(VRegs[0])
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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}
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MIRBuilder.buildInstr(SPIRV::OpReturn);
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return true;
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}
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// Based on the LLVM function attributes, get a SPIR-V FunctionControl.
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static uint32_t getFunctionControl(const Function &F) {
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MemoryEffects MemEffects = F.getMemoryEffects();
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uint32_t FuncControl = static_cast<uint32_t>(SPIRV::FunctionControl::None);
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if (F.hasFnAttribute(Attribute::AttrKind::NoInline))
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::DontInline);
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else if (F.hasFnAttribute(Attribute::AttrKind::AlwaysInline))
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Inline);
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if (MemEffects.doesNotAccessMemory())
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Pure);
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else if (MemEffects.onlyReadsMemory())
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Const);
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return FuncControl;
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}
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static ConstantInt *getConstInt(MDNode *MD, unsigned NumOp) {
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if (MD->getNumOperands() > NumOp) {
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auto *CMeta = dyn_cast<ConstantAsMetadata>(MD->getOperand(NumOp));
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if (CMeta)
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return dyn_cast<ConstantInt>(CMeta->getValue());
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}
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return nullptr;
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}
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// If the function has pointer arguments, we are forced to re-create this
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// function type from the very beginning, changing PointerType by
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// TypedPointerType for each pointer argument. Otherwise, the same `Type*`
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// potentially corresponds to different SPIR-V function type, effectively
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// invalidating logic behind global registry and duplicates tracker.
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static FunctionType *
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fixFunctionTypeIfPtrArgs(SPIRVGlobalRegistry *GR, const Function &F,
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FunctionType *FTy, const SPIRVType *SRetTy,
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const SmallVector<SPIRVType *, 4> &SArgTys) {
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if (F.getParent()->getNamedMetadata("spv.cloned_funcs"))
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return FTy;
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bool hasArgPtrs = false;
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for (auto &Arg : F.args()) {
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// check if it's an instance of a non-typed PointerType
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if (Arg.getType()->isPointerTy()) {
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hasArgPtrs = true;
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break;
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}
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}
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if (!hasArgPtrs) {
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Type *RetTy = FTy->getReturnType();
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// check if it's an instance of a non-typed PointerType
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if (!RetTy->isPointerTy())
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return FTy;
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}
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// re-create function type, using TypedPointerType instead of PointerType to
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// properly trace argument types
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const Type *RetTy = GR->getTypeForSPIRVType(SRetTy);
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SmallVector<Type *, 4> ArgTys;
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for (auto SArgTy : SArgTys)
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ArgTys.push_back(const_cast<Type *>(GR->getTypeForSPIRVType(SArgTy)));
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return FunctionType::get(const_cast<Type *>(RetTy), ArgTys, false);
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}
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// This code restores function args/retvalue types for composite cases
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// because the final types should still be aggregate whereas they're i32
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// during the translation to cope with aggregate flattening etc.
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static FunctionType *getOriginalFunctionType(const Function &F) {
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auto *NamedMD = F.getParent()->getNamedMetadata("spv.cloned_funcs");
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if (NamedMD == nullptr)
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return F.getFunctionType();
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Type *RetTy = F.getFunctionType()->getReturnType();
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SmallVector<Type *, 4> ArgTypes;
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for (auto &Arg : F.args())
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ArgTypes.push_back(Arg.getType());
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auto ThisFuncMDIt =
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std::find_if(NamedMD->op_begin(), NamedMD->op_end(), [&F](MDNode *N) {
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return isa<MDString>(N->getOperand(0)) &&
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cast<MDString>(N->getOperand(0))->getString() == F.getName();
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});
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// TODO: probably one function can have numerous type mutations,
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// so we should support this.
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if (ThisFuncMDIt != NamedMD->op_end()) {
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auto *ThisFuncMD = *ThisFuncMDIt;
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MDNode *MD = dyn_cast<MDNode>(ThisFuncMD->getOperand(1));
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assert(MD && "MDNode operand is expected");
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ConstantInt *Const = getConstInt(MD, 0);
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if (Const) {
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auto *CMeta = dyn_cast<ConstantAsMetadata>(MD->getOperand(1));
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assert(CMeta && "ConstantAsMetadata operand is expected");
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assert(Const->getSExtValue() >= -1);
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// Currently -1 indicates return value, greater values mean
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// argument numbers.
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if (Const->getSExtValue() == -1)
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RetTy = CMeta->getType();
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else
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ArgTypes[Const->getSExtValue()] = CMeta->getType();
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}
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}
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return FunctionType::get(RetTy, ArgTypes, F.isVarArg());
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}
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static SPIRV::AccessQualifier::AccessQualifier
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getArgAccessQual(const Function &F, unsigned ArgIdx) {
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if (F.getCallingConv() != CallingConv::SPIR_KERNEL)
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return SPIRV::AccessQualifier::ReadWrite;
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MDString *ArgAttribute = getOCLKernelArgAccessQual(F, ArgIdx);
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if (!ArgAttribute)
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return SPIRV::AccessQualifier::ReadWrite;
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if (ArgAttribute->getString().compare("read_only") == 0)
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return SPIRV::AccessQualifier::ReadOnly;
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if (ArgAttribute->getString().compare("write_only") == 0)
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return SPIRV::AccessQualifier::WriteOnly;
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return SPIRV::AccessQualifier::ReadWrite;
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}
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static std::vector<SPIRV::Decoration::Decoration>
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getKernelArgTypeQual(const Function &F, unsigned ArgIdx) {
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MDString *ArgAttribute = getOCLKernelArgTypeQual(F, ArgIdx);
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if (ArgAttribute && ArgAttribute->getString().compare("volatile") == 0)
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return {SPIRV::Decoration::Volatile};
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return {};
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}
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static SPIRVType *getArgSPIRVType(const Function &F, unsigned ArgIdx,
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SPIRVGlobalRegistry *GR,
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MachineIRBuilder &MIRBuilder,
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const SPIRVSubtarget &ST) {
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// Read argument's access qualifier from metadata or default.
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SPIRV::AccessQualifier::AccessQualifier ArgAccessQual =
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getArgAccessQual(F, ArgIdx);
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Type *OriginalArgType = getOriginalFunctionType(F)->getParamType(ArgIdx);
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// If OriginalArgType is non-pointer, use the OriginalArgType (the type cannot
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// be legally reassigned later).
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if (!isPointerTy(OriginalArgType))
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return GR->getOrCreateSPIRVType(OriginalArgType, MIRBuilder, ArgAccessQual);
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Argument *Arg = F.getArg(ArgIdx);
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Type *ArgType = Arg->getType();
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if (isTypedPointerTy(ArgType)) {
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SPIRVType *ElementType = GR->getOrCreateSPIRVType(
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cast<TypedPointerType>(ArgType)->getElementType(), MIRBuilder);
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return GR->getOrCreateSPIRVPointerType(
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ElementType, MIRBuilder,
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addressSpaceToStorageClass(getPointerAddressSpace(ArgType), ST));
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}
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// In case OriginalArgType is of untyped pointer type, there are three
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// possibilities:
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// 1) This is a pointer of an LLVM IR element type, passed byval/byref.
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// 2) This is an OpenCL/SPIR-V builtin type if there is spv_assign_type
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// intrinsic assigning a TargetExtType.
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// 3) This is a pointer, try to retrieve pointer element type from a
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// spv_assign_ptr_type intrinsic or otherwise use default pointer element
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// type.
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if (hasPointeeTypeAttr(Arg)) {
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SPIRVType *ElementType =
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GR->getOrCreateSPIRVType(getPointeeTypeByAttr(Arg), MIRBuilder);
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return GR->getOrCreateSPIRVPointerType(
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ElementType, MIRBuilder,
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addressSpaceToStorageClass(getPointerAddressSpace(ArgType), ST));
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}
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for (auto User : Arg->users()) {
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auto *II = dyn_cast<IntrinsicInst>(User);
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// Check if this is spv_assign_type assigning OpenCL/SPIR-V builtin type.
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if (II && II->getIntrinsicID() == Intrinsic::spv_assign_type) {
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MetadataAsValue *VMD = cast<MetadataAsValue>(II->getOperand(1));
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Type *BuiltinType =
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cast<ConstantAsMetadata>(VMD->getMetadata())->getType();
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assert(BuiltinType->isTargetExtTy() && "Expected TargetExtType");
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return GR->getOrCreateSPIRVType(BuiltinType, MIRBuilder, ArgAccessQual);
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}
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// Check if this is spv_assign_ptr_type assigning pointer element type.
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if (!II || II->getIntrinsicID() != Intrinsic::spv_assign_ptr_type)
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continue;
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MetadataAsValue *VMD = cast<MetadataAsValue>(II->getOperand(1));
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Type *ElementTy = cast<ConstantAsMetadata>(VMD->getMetadata())->getType();
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if (isUntypedPointerTy(ElementTy))
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ElementTy =
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TypedPointerType::get(IntegerType::getInt8Ty(II->getContext()),
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getPointerAddressSpace(ElementTy));
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SPIRVType *ElementType = GR->getOrCreateSPIRVType(ElementTy, MIRBuilder);
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return GR->getOrCreateSPIRVPointerType(
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ElementType, MIRBuilder,
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addressSpaceToStorageClass(
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cast<ConstantInt>(II->getOperand(2))->getZExtValue(), ST));
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}
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// Replace PointerType with TypedPointerType to be able to map SPIR-V types to
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// LLVM types in a consistent manner
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if (isUntypedPointerTy(OriginalArgType)) {
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OriginalArgType =
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TypedPointerType::get(Type::getInt8Ty(F.getContext()),
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getPointerAddressSpace(OriginalArgType));
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}
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return GR->getOrCreateSPIRVType(OriginalArgType, MIRBuilder, ArgAccessQual);
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}
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static SPIRV::ExecutionModel::ExecutionModel
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getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
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if (STI.isOpenCLEnv())
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return SPIRV::ExecutionModel::Kernel;
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auto attribute = F.getFnAttribute("hlsl.shader");
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if (!attribute.isValid()) {
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report_fatal_error(
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"This entry point lacks mandatory hlsl.shader attribute.");
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}
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const auto value = attribute.getValueAsString();
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if (value == "compute")
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return SPIRV::ExecutionModel::GLCompute;
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report_fatal_error("This HLSL entry point is not supported by this backend.");
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}
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bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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assert(GR && "Must initialize the SPIRV type registry before lowering args.");
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GR->setCurrentFunc(MIRBuilder.getMF());
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// Get access to information about available extensions
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const SPIRVSubtarget *ST =
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static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
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// Assign types and names to all args, and store their types for later.
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SmallVector<SPIRVType *, 4> ArgTypeVRegs;
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if (VRegs.size() > 0) {
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unsigned i = 0;
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for (const auto &Arg : F.args()) {
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// Currently formal args should use single registers.
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// TODO: handle the case of multiple registers.
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if (VRegs[i].size() > 1)
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return false;
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auto *SpirvTy = getArgSPIRVType(F, i, GR, MIRBuilder, *ST);
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GR->assignSPIRVTypeToVReg(SpirvTy, VRegs[i][0], MIRBuilder.getMF());
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ArgTypeVRegs.push_back(SpirvTy);
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if (Arg.hasName())
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buildOpName(VRegs[i][0], Arg.getName(), MIRBuilder);
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if (isPointerTy(Arg.getType())) {
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auto DerefBytes = static_cast<unsigned>(Arg.getDereferenceableBytes());
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if (DerefBytes != 0)
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::MaxByteOffset, {DerefBytes});
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}
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if (Arg.hasAttribute(Attribute::Alignment)) {
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auto Alignment = static_cast<unsigned>(
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Arg.getAttribute(Attribute::Alignment).getValueAsInt());
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buildOpDecorate(VRegs[i][0], MIRBuilder, SPIRV::Decoration::Alignment,
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{Alignment});
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}
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if (Arg.hasAttribute(Attribute::ReadOnly)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::NoWrite);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::ZExt)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::Zext);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::NoAlias)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::NoAlias);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::ByVal)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::ByVal);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (F.getCallingConv() == CallingConv::SPIR_KERNEL) {
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std::vector<SPIRV::Decoration::Decoration> ArgTypeQualDecs =
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getKernelArgTypeQual(F, i);
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for (SPIRV::Decoration::Decoration Decoration : ArgTypeQualDecs)
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buildOpDecorate(VRegs[i][0], MIRBuilder, Decoration, {});
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}
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MDNode *Node = F.getMetadata("spirv.ParameterDecorations");
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if (Node && i < Node->getNumOperands() &&
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isa<MDNode>(Node->getOperand(i))) {
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MDNode *MD = cast<MDNode>(Node->getOperand(i));
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for (const MDOperand &MDOp : MD->operands()) {
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MDNode *MD2 = dyn_cast<MDNode>(MDOp);
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assert(MD2 && "Metadata operand is expected");
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ConstantInt *Const = getConstInt(MD2, 0);
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assert(Const && "MDOperand should be ConstantInt");
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auto Dec =
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static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
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std::vector<uint32_t> DecVec;
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for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
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ConstantInt *Const = getConstInt(MD2, j);
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assert(Const && "MDOperand should be ConstantInt");
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DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
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}
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buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
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}
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}
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++i;
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}
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}
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auto MRI = MIRBuilder.getMRI();
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Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
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MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
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if (F.isDeclaration())
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GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
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FunctionType *FTy = getOriginalFunctionType(F);
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Type *FRetTy = FTy->getReturnType();
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if (isUntypedPointerTy(FRetTy)) {
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if (Type *FRetElemTy = GR->findDeducedElementType(&F)) {
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TypedPointerType *DerivedTy =
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TypedPointerType::get(FRetElemTy, getPointerAddressSpace(FRetTy));
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GR->addReturnType(&F, DerivedTy);
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FRetTy = DerivedTy;
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}
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}
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SPIRVType *RetTy = GR->getOrCreateSPIRVType(FRetTy, MIRBuilder);
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FTy = fixFunctionTypeIfPtrArgs(GR, F, FTy, RetTy, ArgTypeVRegs);
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SPIRVType *FuncTy = GR->getOrCreateOpTypeFunctionWithArgs(
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FTy, RetTy, ArgTypeVRegs, MIRBuilder);
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uint32_t FuncControl = getFunctionControl(F);
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// Add OpFunction instruction
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MachineInstrBuilder MB = MIRBuilder.buildInstr(SPIRV::OpFunction)
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.addDef(FuncVReg)
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.addUse(GR->getSPIRVTypeID(RetTy))
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.addImm(FuncControl)
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.addUse(GR->getSPIRVTypeID(FuncTy));
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GR->recordFunctionDefinition(&F, &MB.getInstr()->getOperand(0));
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// Add OpFunctionParameter instructions
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int i = 0;
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for (const auto &Arg : F.args()) {
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assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
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MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
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MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
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.addDef(VRegs[i][0])
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.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
|
|
if (F.isDeclaration())
|
|
GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]);
|
|
i++;
|
|
}
|
|
// Name the function.
|
|
if (F.hasName())
|
|
buildOpName(FuncVReg, F.getName(), MIRBuilder);
|
|
|
|
// Handle entry points and function linkage.
|
|
if (isEntryPoint(F)) {
|
|
const auto &STI = MIRBuilder.getMF().getSubtarget<SPIRVSubtarget>();
|
|
auto executionModel = getExecutionModel(STI, F);
|
|
auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint)
|
|
.addImm(static_cast<uint32_t>(executionModel))
|
|
.addUse(FuncVReg);
|
|
addStringImm(F.getName(), MIB);
|
|
} else if (F.getLinkage() == GlobalValue::LinkageTypes::ExternalLinkage ||
|
|
F.getLinkage() == GlobalValue::LinkOnceODRLinkage) {
|
|
SPIRV::LinkageType::LinkageType LnkTy =
|
|
F.isDeclaration()
|
|
? SPIRV::LinkageType::Import
|
|
: (F.getLinkage() == GlobalValue::LinkOnceODRLinkage &&
|
|
ST->canUseExtension(
|
|
SPIRV::Extension::SPV_KHR_linkonce_odr)
|
|
? SPIRV::LinkageType::LinkOnceODR
|
|
: SPIRV::LinkageType::Export);
|
|
buildOpDecorate(FuncVReg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,
|
|
{static_cast<uint32_t>(LnkTy)}, F.getGlobalIdentifier());
|
|
}
|
|
|
|
// Handle function pointers decoration
|
|
bool hasFunctionPointers =
|
|
ST->canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers);
|
|
if (hasFunctionPointers) {
|
|
if (F.hasFnAttribute("referenced-indirectly")) {
|
|
assert((F.getCallingConv() != CallingConv::SPIR_KERNEL) &&
|
|
"Unexpected 'referenced-indirectly' attribute of the kernel "
|
|
"function");
|
|
buildOpDecorate(FuncVReg, MIRBuilder,
|
|
SPIRV::Decoration::ReferencedIndirectlyINTEL, {});
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Used to postpone producing of indirect function pointer types after all
|
|
// indirect calls info is collected
|
|
// TODO:
|
|
// - add a topological sort of IndirectCalls to ensure the best types knowledge
|
|
// - we may need to fix function formal parameter types if they are opaque
|
|
// pointers used as function pointers in these indirect calls
|
|
void SPIRVCallLowering::produceIndirectPtrTypes(
|
|
MachineIRBuilder &MIRBuilder) const {
|
|
// Create indirect call data types if any
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
for (auto const &IC : IndirectCalls) {
|
|
SPIRVType *SpirvRetTy = GR->getOrCreateSPIRVType(IC.RetTy, MIRBuilder);
|
|
SmallVector<SPIRVType *, 4> SpirvArgTypes;
|
|
for (size_t i = 0; i < IC.ArgTys.size(); ++i) {
|
|
SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(IC.ArgTys[i], MIRBuilder);
|
|
SpirvArgTypes.push_back(SPIRVTy);
|
|
if (!GR->getSPIRVTypeForVReg(IC.ArgRegs[i]))
|
|
GR->assignSPIRVTypeToVReg(SPIRVTy, IC.ArgRegs[i], MF);
|
|
}
|
|
// SPIR-V function type:
|
|
FunctionType *FTy =
|
|
FunctionType::get(const_cast<Type *>(IC.RetTy), IC.ArgTys, false);
|
|
SPIRVType *SpirvFuncTy = GR->getOrCreateOpTypeFunctionWithArgs(
|
|
FTy, SpirvRetTy, SpirvArgTypes, MIRBuilder);
|
|
// SPIR-V pointer to function type:
|
|
SPIRVType *IndirectFuncPtrTy = GR->getOrCreateSPIRVPointerType(
|
|
SpirvFuncTy, MIRBuilder, SPIRV::StorageClass::Function);
|
|
// Correct the Callee type
|
|
GR->assignSPIRVTypeToVReg(IndirectFuncPtrTy, IC.Callee, MF);
|
|
}
|
|
}
|
|
|
|
bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
|
|
CallLoweringInfo &Info) const {
|
|
// Currently call returns should have single vregs.
|
|
// TODO: handle the case of multiple registers.
|
|
if (Info.OrigRet.Regs.size() > 1)
|
|
return false;
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
GR->setCurrentFunc(MF);
|
|
const Function *CF = nullptr;
|
|
std::string DemangledName;
|
|
const Type *OrigRetTy = Info.OrigRet.Ty;
|
|
|
|
// Emit a regular OpFunctionCall. If it's an externally declared function,
|
|
// be sure to emit its type and function declaration here. It will be hoisted
|
|
// globally later.
|
|
if (Info.Callee.isGlobal()) {
|
|
std::string FuncName = Info.Callee.getGlobal()->getName().str();
|
|
DemangledName = getOclOrSpirvBuiltinDemangledName(FuncName);
|
|
CF = dyn_cast_or_null<const Function>(Info.Callee.getGlobal());
|
|
// TODO: support constexpr casts and indirect calls.
|
|
if (CF == nullptr)
|
|
return false;
|
|
if (FunctionType *FTy = getOriginalFunctionType(*CF)) {
|
|
OrigRetTy = FTy->getReturnType();
|
|
if (isUntypedPointerTy(OrigRetTy)) {
|
|
if (auto *DerivedRetTy = GR->findReturnType(CF))
|
|
OrigRetTy = DerivedRetTy;
|
|
}
|
|
}
|
|
}
|
|
|
|
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
|
|
Register ResVReg =
|
|
Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0];
|
|
const auto *ST = static_cast<const SPIRVSubtarget *>(&MF.getSubtarget());
|
|
|
|
bool isFunctionDecl = CF && CF->isDeclaration();
|
|
bool canUseOpenCL = ST->canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std);
|
|
bool canUseGLSL = ST->canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450);
|
|
assert(canUseGLSL != canUseOpenCL &&
|
|
"Scenario where both sets are enabled is not supported.");
|
|
|
|
if (isFunctionDecl && !DemangledName.empty() &&
|
|
(canUseGLSL || canUseOpenCL)) {
|
|
SmallVector<Register, 8> ArgVRegs;
|
|
for (auto Arg : Info.OrigArgs) {
|
|
assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
|
|
ArgVRegs.push_back(Arg.Regs[0]);
|
|
SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
|
|
if (!GR->getSPIRVTypeForVReg(Arg.Regs[0]))
|
|
GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MF);
|
|
}
|
|
auto instructionSet = canUseOpenCL ? SPIRV::InstructionSet::OpenCL_std
|
|
: SPIRV::InstructionSet::GLSL_std_450;
|
|
if (auto Res =
|
|
SPIRV::lowerBuiltin(DemangledName, instructionSet, MIRBuilder,
|
|
ResVReg, OrigRetTy, ArgVRegs, GR))
|
|
return *Res;
|
|
}
|
|
|
|
if (isFunctionDecl && !GR->find(CF, &MF).isValid()) {
|
|
// Emit the type info and forward function declaration to the first MBB
|
|
// to ensure VReg definition dependencies are valid across all MBBs.
|
|
MachineIRBuilder FirstBlockBuilder;
|
|
FirstBlockBuilder.setMF(MF);
|
|
FirstBlockBuilder.setMBB(*MF.getBlockNumbered(0));
|
|
|
|
SmallVector<ArrayRef<Register>, 8> VRegArgs;
|
|
SmallVector<SmallVector<Register, 1>, 8> ToInsert;
|
|
for (const Argument &Arg : CF->args()) {
|
|
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
|
|
continue; // Don't handle zero sized types.
|
|
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
|
|
MRI->setRegClass(Reg, &SPIRV::IDRegClass);
|
|
ToInsert.push_back({Reg});
|
|
VRegArgs.push_back(ToInsert.back());
|
|
}
|
|
// TODO: Reuse FunctionLoweringInfo
|
|
FunctionLoweringInfo FuncInfo;
|
|
lowerFormalArguments(FirstBlockBuilder, *CF, VRegArgs, FuncInfo);
|
|
}
|
|
|
|
unsigned CallOp;
|
|
if (Info.CB->isIndirectCall()) {
|
|
if (!ST->canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers))
|
|
report_fatal_error("An indirect call is encountered but SPIR-V without "
|
|
"extensions does not support it",
|
|
false);
|
|
// Set instruction operation according to SPV_INTEL_function_pointers
|
|
CallOp = SPIRV::OpFunctionPointerCallINTEL;
|
|
// Collect information about the indirect call to support possible
|
|
// specification of opaque ptr types of parent function's parameters
|
|
Register CalleeReg = Info.Callee.getReg();
|
|
if (CalleeReg.isValid()) {
|
|
SPIRVCallLowering::SPIRVIndirectCall IndirectCall;
|
|
IndirectCall.Callee = CalleeReg;
|
|
IndirectCall.RetTy = OrigRetTy;
|
|
for (const auto &Arg : Info.OrigArgs) {
|
|
assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
|
|
IndirectCall.ArgTys.push_back(Arg.Ty);
|
|
IndirectCall.ArgRegs.push_back(Arg.Regs[0]);
|
|
}
|
|
IndirectCalls.push_back(IndirectCall);
|
|
}
|
|
} else {
|
|
// Emit a regular OpFunctionCall
|
|
CallOp = SPIRV::OpFunctionCall;
|
|
}
|
|
|
|
// Make sure there's a valid return reg, even for functions returning void.
|
|
if (!ResVReg.isValid())
|
|
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
|
|
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);
|
|
|
|
// Emit the call instruction and its args.
|
|
auto MIB = MIRBuilder.buildInstr(CallOp)
|
|
.addDef(ResVReg)
|
|
.addUse(GR->getSPIRVTypeID(RetType))
|
|
.add(Info.Callee);
|
|
|
|
for (const auto &Arg : Info.OrigArgs) {
|
|
// Currently call args should have single vregs.
|
|
if (Arg.Regs.size() > 1)
|
|
return false;
|
|
MIB.addUse(Arg.Regs[0]);
|
|
}
|
|
return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(),
|
|
*ST->getRegBankInfo());
|
|
}
|