cfca977427
Re-land 61b2a0e333. Some Windows builds
were failing because AArch64TargetParserDef.inc is a generated header
which is included transitively into some clang components, but this
information is not available to the build system and therefore there is
a missing edge in the dependency graph. This patch incorporates the
fixes described in ac1ffd3caca12c254e0b8c847aa8ce8e51b6cfbf/D142403.
Thanks to ExtensionSet::toLLVMFeatureList, all values of ArchExtKind
should correspond to a particular -target-feature. The valid values of
-target-feature are in turn defined by SubtargetFeature defs.
Therefore we can generate ArchExtKind from the tablegen data. This is
done by adding an Extension class which derives from SubtargetFeature.
Because the Has* FieldNames do not always correspond to the AEK_
names ("extensions", as defined in TargetParser), and AEK_ names do
not always correspond to -march strings, some additional enum entries
have been added to remap the names. I have renamed these to make the
naming consistent, but split them into a separate PR to keep the diff
reasonable (#90320)
75 lines
3.0 KiB
C++
75 lines
3.0 KiB
C++
//===- ARMTargetDefEmitter.cpp - Generate data about ARM Architectures ----===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This tablegen backend exports information about CPUs, FPUs, architectures,
|
|
// and features into a common format that can be used by both TargetParser and
|
|
// the ARM and AArch64 backends.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/ADT/StringSet.h"
|
|
#include "llvm/TableGen/Record.h"
|
|
#include "llvm/TableGen/TableGenBackend.h"
|
|
|
|
using namespace llvm;
|
|
|
|
static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
|
|
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
|
|
|
|
// Look through all SubtargetFeature defs with the given FieldName, and
|
|
// collect the set of all Values that that FieldName is set to.
|
|
auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
|
|
llvm::StringSet<> Set;
|
|
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
|
|
if (Rec->getValueAsString("FieldName") == FieldName) {
|
|
Set.insert(Rec->getValueAsString("Value"));
|
|
}
|
|
}
|
|
return Set;
|
|
};
|
|
|
|
// The ARMProcFamilyEnum values are initialised by SubtargetFeature defs
|
|
// which set the ARMProcFamily field. We can generate the enum from these defs
|
|
// which look like this:
|
|
//
|
|
// def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
|
|
// "Cortex-A5 ARM processors", []>;
|
|
OS << "#ifndef ARM_PROCESSOR_FAMILY\n"
|
|
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
|
|
<< "#endif\n\n";
|
|
const StringSet<> ARMProcFamilyVals =
|
|
gatherSubtargetFeatureFieldValues("ARMProcFamily");
|
|
for (const StringRef &Family : ARMProcFamilyVals.keys())
|
|
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
|
|
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
|
|
|
|
OS << "#ifndef ARM_ARCHITECTURE\n"
|
|
<< "#define ARM_ARCHITECTURE(ENUM)\n"
|
|
<< "#endif\n\n";
|
|
// This should correspond to instances of the Architecture tablegen class.
|
|
const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
|
|
for (const StringRef &Arch : ARMArchVals.keys())
|
|
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
|
|
OS << "\n#undef ARM_ARCHITECTURE\n\n";
|
|
|
|
// Emit information for each defined Extension; used to build ArmExtKind.
|
|
OS << "#ifndef ARM_EXTENSION\n"
|
|
<< "#define ARM_EXTENSION(NAME, ENUM)\n"
|
|
<< "#endif\n\n";
|
|
for (const Record *Rec : RK.getAllDerivedDefinitions("Extension")) {
|
|
StringRef Name = Rec->getValueAsString("Name");
|
|
std::string Enum = Rec->getValueAsString("ArchExtKindSpelling").upper();
|
|
OS << "ARM_EXTENSION(" << Name << ", " << Enum << ")\n";
|
|
}
|
|
OS << "\n#undef ARM_EXTENSION\n\n";
|
|
}
|
|
|
|
static TableGen::Emitter::Opt
|
|
X("gen-arm-target-def", EmitARMTargetDef,
|
|
"Generate the ARM or AArch64 Architecture information header.");
|