Philip Reames d5a4dad206 Fix a *nasty* miscompile in experimental unordered atomic lowering ...

This is an omission in rL371441.  Loads which happened to be unordered weren't being added to the PendingLoad set, and thus weren't be ordered w/respect to side effects which followed before the end of the block.

Included test case is how I spotted this.  We had an atomic load being folded into a using instruction after a fence that load was supposed to be ordered with.  I'm sure it showed up a bunch of other ways as well.

Spotted via manual inspecting of assembly differences in a corpus w/and w/o the new experimental mode.  Finding this with testing would have been "unpleasant".  

llvm-svn: 373814

2019-10-05 00:32:10 +00:00

..

CMakeLists.txt

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DAGCombiner.cpp

[DAGCombiner] add operation legality checks before creating shift ops (PR43542)

2019-10-03 21:34:04 +00:00

FastISel.cpp

[FastISel] Fix insertion of unconditional branches during FastISel

2019-09-20 13:22:59 +00:00

FunctionLoweringInfo.cpp

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

2019-08-01 23:27:28 +00:00

InstrEmitter.cpp

[TargetRegisterInfo] Remove SVT argument from getCommonSubClass.

2019-09-13 05:24:37 +00:00

InstrEmitter.h

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LegalizeDAG.cpp

[TargetLowering] Make allowsMemoryAccess methode virtual.

2019-09-26 00:16:01 +00:00

LegalizeFloatTypes.cpp

[LegalizeTypes] Remove code for softening a float type to itself.

2019-09-12 05:55:14 +00:00

LegalizeIntegerTypes.cpp

[Intrinsic] Add the llvm.umul.fix.sat intrinsic

2019-09-07 12:16:14 +00:00

LegalizeTypes.cpp

[LegalizeTypes] Remove code for softening a float type to itself.

2019-09-12 05:55:14 +00:00

LegalizeTypes.h

[LegalizeTypes] Remove code for softening a float type to itself.

2019-09-12 05:55:14 +00:00

LegalizeTypesGeneric.cpp

[LegalizeTypes] Check for already split condition before calilng SplitVecRes_SETCC in SplitRes_SELECT.

2019-10-02 22:34:49 +00:00

LegalizeVectorOps.cpp

[SelectionDAG] Remove ISD::FP_ROUND_INREG

2019-09-09 17:54:44 +00:00

LegalizeVectorTypes.cpp

[SDAG] Update generic code to conservatively check for isAtomic in addition to isVolatile

2019-09-12 22:49:17 +00:00

LLVMBuild.txt

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ResourcePriorityQueue.cpp

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ScheduleDAGFast.cpp

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

2019-08-01 23:27:28 +00:00

ScheduleDAGRRList.cpp

[ScheduleDAG] When a node is cloned, add an edge between the nodes.

2019-10-04 19:51:40 +00:00

ScheduleDAGSDNodes.cpp

Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM

2019-08-15 19:22:08 +00:00

ScheduleDAGSDNodes.h

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ScheduleDAGVLIW.cpp

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SDNodeDbgValue.h

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SelectionDAG.cpp

Support MemoryLocation::UnknownSize in TargetLowering::IntrinsicInfo

2019-09-30 14:44:24 +00:00

SelectionDAGAddressAnalysis.cpp

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SelectionDAGBuilder.cpp

Fix a *nasty* miscompile in experimental unordered atomic lowering

2019-10-05 00:32:10 +00:00

SelectionDAGBuilder.h

[llvm] Migrate llvm::make_unique to std::make_unique

2019-08-15 15:54:37 +00:00

SelectionDAGDumper.cpp

[SelectionDAG] Remove ISD::FP_ROUND_INREG

2019-09-09 17:54:44 +00:00

SelectionDAGISel.cpp

TLI: Remove DAG argument from getRegisterByName

2019-10-01 01:44:39 +00:00

SelectionDAGPrinter.cpp

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SelectionDAGTargetInfo.cpp

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StatepointLowering.cpp

[Statepoints] Fix overalignment of loads in no-realign-stack functions

2019-08-02 20:17:37 +00:00

StatepointLowering.h

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TargetLowering.cpp

[DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (PR42863)

2019-10-01 15:32:04 +00:00