bbd54e08b0
…unction (#91321)"
This reapplies fd1bd53ba5, which was
reverted due to a test failure on aarch64/windows. The failure was
caused by a combination of several factors:
- clang targeting aarch64-windows (unlike msvc, and unlike clang
targeting other aarch64 platforms) defaults to -fomit-frame-pointers
- lldb's code for looking up register values for `<same>` unwind rules
is recursive
- the test binary creates a very long chain of fp-less function frames
(it manages to fit about 22k frames before it blows its stack)
Together, these things have caused lldb to recreate the same deep
recursion when unwinding through this, and blow its own stack as well.
Since lldb frames are larger, about 4k frames like this was sufficient
to trigger the stack overflow.
This version of the patch works around this problem by increasing the
frame size of the test binary, thereby causing it to blow its stack
sooner. This doesn't fix the issue -- the same problem can occur with a
real binary -- but it's not very likely, as it requires an infinite
recursion in a simple (so it doesn't use the frame pointer) function
with a very small frame (so you can fit a lot of them on the stack).
A more principled fix would be to make lldb's lookup code non-recursive,
but I believe that's out of scope for this patch.
The original patch description follows:
A leaf function may not store the link register to stack, but we it can
still end up being a non-zero frame if it gets interrupted by a signal.
Currently, we were unable to unwind past this function because we could
not read the link register value.
To make this work, this patch:
- changes the function-entry unwind plan to include the `fp|lr = <same>`
rules. This in turn necessitated an adjustment in the generic
instruction emulation logic to ensure that `lr=[sp-X]` can override the
`<same>` rule.
- allows the `<same>` rule for pc and lr in all
`m_all_registers_available` frames (and not just frame zero).
The test verifies that we can unwind in a situation like this, and that
the backtrace matches the one we computed before getting a signal.
694 lines
28 KiB
C++
694 lines
28 KiB
C++
//===-- UnwindAssemblyInstEmulation.cpp -----------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "UnwindAssemblyInstEmulation.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/Disassembler.h"
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#include "lldb/Core/DumpDataExtractor.h"
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#include "lldb/Core/DumpRegisterValue.h"
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#include "lldb/Core/FormatEntity.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Target/ExecutionContext.h"
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#include "lldb/Target/Process.h"
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#include "lldb/Target/Target.h"
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#include "lldb/Target/Thread.h"
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#include "lldb/Utility/ArchSpec.h"
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#include "lldb/Utility/DataBufferHeap.h"
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#include "lldb/Utility/DataExtractor.h"
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#include "lldb/Utility/LLDBLog.h"
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#include "lldb/Utility/Log.h"
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#include "lldb/Utility/Status.h"
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#include "lldb/Utility/StreamString.h"
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using namespace lldb;
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using namespace lldb_private;
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LLDB_PLUGIN_DEFINE(UnwindAssemblyInstEmulation)
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// UnwindAssemblyInstEmulation method definitions
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bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
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AddressRange &range, Thread &thread, UnwindPlan &unwind_plan) {
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std::vector<uint8_t> function_text(range.GetByteSize());
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ProcessSP process_sp(thread.GetProcess());
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if (process_sp) {
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Status error;
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const bool force_live_memory = true;
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if (process_sp->GetTarget().ReadMemory(
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range.GetBaseAddress(), function_text.data(), range.GetByteSize(),
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error, force_live_memory) != range.GetByteSize()) {
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return false;
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}
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}
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return GetNonCallSiteUnwindPlanFromAssembly(
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range, function_text.data(), function_text.size(), unwind_plan);
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}
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bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
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AddressRange &range, uint8_t *opcode_data, size_t opcode_size,
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UnwindPlan &unwind_plan) {
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if (opcode_data == nullptr || opcode_size == 0)
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return false;
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if (range.GetByteSize() > 0 && range.GetBaseAddress().IsValid() &&
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m_inst_emulator_up.get()) {
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// The instruction emulation subclass setup the unwind plan for the first
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// instruction.
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m_inst_emulator_up->CreateFunctionEntryUnwind(unwind_plan);
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// CreateFunctionEntryUnwind should have created the first row. If it
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// doesn't, then we are done.
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if (unwind_plan.GetRowCount() == 0)
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return false;
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const bool prefer_file_cache = true;
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DisassemblerSP disasm_sp(Disassembler::DisassembleBytes(
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m_arch, nullptr, nullptr, range.GetBaseAddress(), opcode_data,
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opcode_size, 99999, prefer_file_cache));
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Log *log = GetLog(LLDBLog::Unwind);
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if (disasm_sp) {
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m_range_ptr = ⦥
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m_unwind_plan_ptr = &unwind_plan;
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const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
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const bool show_address = true;
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const bool show_bytes = true;
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const bool show_control_flow_kind = false;
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m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
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unwind_plan.GetRegisterKind(), unwind_plan.GetInitialCFARegister());
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m_fp_is_cfa = false;
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m_register_values.clear();
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m_pushed_regs.clear();
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// Initialize the CFA with a known value. In the 32 bit case it will be
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// 0x80000000, and in the 64 bit case 0x8000000000000000. We use the
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// address byte size to be safe for any future address sizes
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m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
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RegisterValue cfa_reg_value;
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cfa_reg_value.SetUInt(m_initial_sp, m_cfa_reg_info.byte_size);
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SetRegisterValue(m_cfa_reg_info, cfa_reg_value);
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const InstructionList &inst_list = disasm_sp->GetInstructionList();
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const size_t num_instructions = inst_list.GetSize();
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if (num_instructions > 0) {
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Instruction *inst = inst_list.GetInstructionAtIndex(0).get();
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const lldb::addr_t base_addr = inst->GetAddress().GetFileAddress();
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// Map for storing the unwind plan row and the value of the registers
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// at a given offset. When we see a forward branch we add a new entry
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// to this map with the actual unwind plan row and register context for
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// the target address of the branch as the current data have to be
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// valid for the target address of the branch too if we are in the same
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// function.
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std::map<lldb::addr_t, std::pair<UnwindPlan::RowSP, RegisterValueMap>>
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saved_unwind_states;
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// Make a copy of the current instruction Row and save it in m_curr_row
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// so we can add updates as we process the instructions.
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UnwindPlan::RowSP last_row = unwind_plan.GetLastRow();
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UnwindPlan::Row *newrow = new UnwindPlan::Row;
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if (last_row.get())
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*newrow = *last_row.get();
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m_curr_row.reset(newrow);
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// Add the initial state to the save list with offset 0.
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saved_unwind_states.insert({0, {last_row, m_register_values}});
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// cache the stack pointer register number (in whatever register
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// numbering this UnwindPlan uses) for quick reference during
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// instruction parsing.
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RegisterInfo sp_reg_info = *m_inst_emulator_up->GetRegisterInfo(
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eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
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// The architecture dependent condition code of the last processed
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// instruction.
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EmulateInstruction::InstructionCondition last_condition =
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EmulateInstruction::UnconditionalCondition;
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lldb::addr_t condition_block_start_offset = 0;
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for (size_t idx = 0; idx < num_instructions; ++idx) {
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m_curr_row_modified = false;
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m_forward_branch_offset = 0;
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inst = inst_list.GetInstructionAtIndex(idx).get();
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if (inst) {
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lldb::addr_t current_offset =
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inst->GetAddress().GetFileAddress() - base_addr;
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auto it = saved_unwind_states.upper_bound(current_offset);
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assert(it != saved_unwind_states.begin() &&
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"Unwind row for the function entry missing");
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--it; // Move it to the row corresponding to the current offset
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// If the offset of m_curr_row don't match with the offset we see
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// in saved_unwind_states then we have to update m_curr_row and
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// m_register_values based on the saved values. It is happening
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// after we processed an epilogue and a return to caller
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// instruction.
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if (it->second.first->GetOffset() != m_curr_row->GetOffset()) {
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UnwindPlan::Row *newrow = new UnwindPlan::Row;
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*newrow = *it->second.first;
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m_curr_row.reset(newrow);
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m_register_values = it->second.second;
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// re-set the CFA register ivars to match the
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// new m_curr_row.
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if (sp_reg_info.name &&
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m_curr_row->GetCFAValue().IsRegisterPlusOffset()) {
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uint32_t row_cfa_regnum =
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m_curr_row->GetCFAValue().GetRegisterNumber();
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lldb::RegisterKind row_kind =
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m_unwind_plan_ptr->GetRegisterKind();
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// set m_cfa_reg_info to the row's CFA reg.
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m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
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row_kind, row_cfa_regnum);
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// set m_fp_is_cfa.
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if (sp_reg_info.kinds[row_kind] == row_cfa_regnum)
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m_fp_is_cfa = false;
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else
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m_fp_is_cfa = true;
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}
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}
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m_inst_emulator_up->SetInstruction(inst->GetOpcode(),
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inst->GetAddress(), nullptr);
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if (last_condition !=
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m_inst_emulator_up->GetInstructionCondition()) {
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if (m_inst_emulator_up->GetInstructionCondition() !=
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EmulateInstruction::UnconditionalCondition &&
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saved_unwind_states.count(current_offset) == 0) {
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// If we don't have a saved row for the current offset then
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// save our current state because we will have to restore it
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// after the conditional block.
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auto new_row =
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std::make_shared<UnwindPlan::Row>(*m_curr_row.get());
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saved_unwind_states.insert(
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{current_offset, {new_row, m_register_values}});
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}
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// If the last instruction was conditional with a different
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// condition then the then current condition then restore the
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// condition.
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if (last_condition !=
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EmulateInstruction::UnconditionalCondition) {
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const auto &saved_state =
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saved_unwind_states.at(condition_block_start_offset);
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m_curr_row =
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std::make_shared<UnwindPlan::Row>(*saved_state.first);
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m_curr_row->SetOffset(current_offset);
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m_register_values = saved_state.second;
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// re-set the CFA register ivars to match the
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// new m_curr_row.
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if (sp_reg_info.name &&
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m_curr_row->GetCFAValue().IsRegisterPlusOffset()) {
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uint32_t row_cfa_regnum =
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m_curr_row->GetCFAValue().GetRegisterNumber();
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lldb::RegisterKind row_kind =
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m_unwind_plan_ptr->GetRegisterKind();
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// set m_cfa_reg_info to the row's CFA reg.
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m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
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row_kind, row_cfa_regnum);
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// set m_fp_is_cfa.
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if (sp_reg_info.kinds[row_kind] == row_cfa_regnum)
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m_fp_is_cfa = false;
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else
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m_fp_is_cfa = true;
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}
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bool replace_existing =
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true; // The last instruction might already
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// created a row for this offset and
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// we want to overwrite it.
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unwind_plan.InsertRow(
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std::make_shared<UnwindPlan::Row>(*m_curr_row),
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replace_existing);
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}
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// We are starting a new conditional block at the actual offset
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condition_block_start_offset = current_offset;
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}
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if (log && log->GetVerbose()) {
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StreamString strm;
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lldb_private::FormatEntity::Entry format;
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FormatEntity::Parse("${frame.pc}: ", format);
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inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize(), show_address,
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show_bytes, show_control_flow_kind, nullptr, nullptr,
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nullptr, &format, 0);
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log->PutString(strm.GetString());
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}
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last_condition = m_inst_emulator_up->GetInstructionCondition();
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m_inst_emulator_up->EvaluateInstruction(
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eEmulateInstructionOptionIgnoreConditions);
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// If the current instruction is a branch forward then save the
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// current CFI information for the offset where we are branching.
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if (m_forward_branch_offset != 0 &&
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range.ContainsFileAddress(inst->GetAddress().GetFileAddress() +
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m_forward_branch_offset)) {
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auto newrow =
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std::make_shared<UnwindPlan::Row>(*m_curr_row.get());
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newrow->SetOffset(current_offset + m_forward_branch_offset);
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saved_unwind_states.insert(
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{current_offset + m_forward_branch_offset,
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{newrow, m_register_values}});
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unwind_plan.InsertRow(newrow);
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}
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// Were there any changes to the CFI while evaluating this
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// instruction?
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if (m_curr_row_modified) {
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// Save the modified row if we don't already have a CFI row in
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// the current address
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if (saved_unwind_states.count(
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current_offset + inst->GetOpcode().GetByteSize()) == 0) {
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m_curr_row->SetOffset(current_offset +
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inst->GetOpcode().GetByteSize());
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unwind_plan.InsertRow(m_curr_row);
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saved_unwind_states.insert(
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{current_offset + inst->GetOpcode().GetByteSize(),
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{m_curr_row, m_register_values}});
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// Allocate a new Row for m_curr_row, copy the current state
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// into it
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UnwindPlan::Row *newrow = new UnwindPlan::Row;
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*newrow = *m_curr_row.get();
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m_curr_row.reset(newrow);
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}
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}
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}
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}
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}
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}
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if (log && log->GetVerbose()) {
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StreamString strm;
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lldb::addr_t base_addr = range.GetBaseAddress().GetFileAddress();
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strm.Printf("Resulting unwind rows for [0x%" PRIx64 " - 0x%" PRIx64 "):",
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base_addr, base_addr + range.GetByteSize());
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unwind_plan.Dump(strm, nullptr, base_addr);
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log->PutString(strm.GetString());
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}
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return unwind_plan.GetRowCount() > 0;
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}
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return false;
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}
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bool UnwindAssemblyInstEmulation::AugmentUnwindPlanFromCallSite(
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AddressRange &func, Thread &thread, UnwindPlan &unwind_plan) {
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return false;
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}
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bool UnwindAssemblyInstEmulation::GetFastUnwindPlan(AddressRange &func,
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Thread &thread,
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UnwindPlan &unwind_plan) {
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return false;
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}
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bool UnwindAssemblyInstEmulation::FirstNonPrologueInsn(
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AddressRange &func, const ExecutionContext &exe_ctx,
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Address &first_non_prologue_insn) {
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return false;
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}
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UnwindAssembly *
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UnwindAssemblyInstEmulation::CreateInstance(const ArchSpec &arch) {
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std::unique_ptr<EmulateInstruction> inst_emulator_up(
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EmulateInstruction::FindPlugin(arch, eInstructionTypePrologueEpilogue,
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nullptr));
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// Make sure that all prologue instructions are handled
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if (inst_emulator_up)
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return new UnwindAssemblyInstEmulation(arch, inst_emulator_up.release());
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return nullptr;
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}
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void UnwindAssemblyInstEmulation::Initialize() {
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PluginManager::RegisterPlugin(GetPluginNameStatic(),
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GetPluginDescriptionStatic(), CreateInstance);
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}
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void UnwindAssemblyInstEmulation::Terminate() {
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PluginManager::UnregisterPlugin(CreateInstance);
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}
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llvm::StringRef UnwindAssemblyInstEmulation::GetPluginDescriptionStatic() {
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return "Instruction emulation based unwind information.";
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}
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uint64_t UnwindAssemblyInstEmulation::MakeRegisterKindValuePair(
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const RegisterInfo ®_info) {
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lldb::RegisterKind reg_kind;
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uint32_t reg_num;
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if (EmulateInstruction::GetBestRegisterKindAndNumber(®_info, reg_kind,
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reg_num))
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return (uint64_t)reg_kind << 24 | reg_num;
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return 0ull;
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}
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void UnwindAssemblyInstEmulation::SetRegisterValue(
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const RegisterInfo ®_info, const RegisterValue ®_value) {
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m_register_values[MakeRegisterKindValuePair(reg_info)] = reg_value;
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}
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bool UnwindAssemblyInstEmulation::GetRegisterValue(const RegisterInfo ®_info,
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RegisterValue ®_value) {
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const uint64_t reg_id = MakeRegisterKindValuePair(reg_info);
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RegisterValueMap::const_iterator pos = m_register_values.find(reg_id);
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if (pos != m_register_values.end()) {
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reg_value = pos->second;
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return true; // We had a real value that comes from an opcode that wrote
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// to it...
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}
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// We are making up a value that is recognizable...
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reg_value.SetUInt(reg_id, reg_info.byte_size);
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return false;
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}
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size_t UnwindAssemblyInstEmulation::ReadMemory(
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EmulateInstruction *instruction, void *baton,
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const EmulateInstruction::Context &context, lldb::addr_t addr, void *dst,
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size_t dst_len) {
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Log *log = GetLog(LLDBLog::Unwind);
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if (log && log->GetVerbose()) {
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StreamString strm;
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strm.Printf(
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"UnwindAssemblyInstEmulation::ReadMemory (addr = 0x%16.16" PRIx64
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", dst = %p, dst_len = %" PRIu64 ", context = ",
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addr, dst, (uint64_t)dst_len);
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context.Dump(strm, instruction);
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log->PutString(strm.GetString());
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}
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memset(dst, 0, dst_len);
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return dst_len;
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}
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size_t UnwindAssemblyInstEmulation::WriteMemory(
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EmulateInstruction *instruction, void *baton,
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const EmulateInstruction::Context &context, lldb::addr_t addr,
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const void *dst, size_t dst_len) {
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if (baton && dst && dst_len)
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return ((UnwindAssemblyInstEmulation *)baton)
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->WriteMemory(instruction, context, addr, dst, dst_len);
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return 0;
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}
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size_t UnwindAssemblyInstEmulation::WriteMemory(
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EmulateInstruction *instruction, const EmulateInstruction::Context &context,
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lldb::addr_t addr, const void *dst, size_t dst_len) {
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DataExtractor data(dst, dst_len,
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instruction->GetArchitecture().GetByteOrder(),
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instruction->GetArchitecture().GetAddressByteSize());
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Log *log = GetLog(LLDBLog::Unwind);
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if (log && log->GetVerbose()) {
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StreamString strm;
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strm.PutCString("UnwindAssemblyInstEmulation::WriteMemory (");
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DumpDataExtractor(data, &strm, 0, eFormatBytes, 1, dst_len, UINT32_MAX,
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addr, 0, 0);
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strm.PutCString(", context = ");
|
|
context.Dump(strm, instruction);
|
|
log->PutString(strm.GetString());
|
|
}
|
|
|
|
switch (context.type) {
|
|
default:
|
|
case EmulateInstruction::eContextInvalid:
|
|
case EmulateInstruction::eContextReadOpcode:
|
|
case EmulateInstruction::eContextImmediate:
|
|
case EmulateInstruction::eContextAdjustBaseRegister:
|
|
case EmulateInstruction::eContextRegisterPlusOffset:
|
|
case EmulateInstruction::eContextAdjustPC:
|
|
case EmulateInstruction::eContextRegisterStore:
|
|
case EmulateInstruction::eContextRegisterLoad:
|
|
case EmulateInstruction::eContextRelativeBranchImmediate:
|
|
case EmulateInstruction::eContextAbsoluteBranchRegister:
|
|
case EmulateInstruction::eContextSupervisorCall:
|
|
case EmulateInstruction::eContextTableBranchReadMemory:
|
|
case EmulateInstruction::eContextWriteRegisterRandomBits:
|
|
case EmulateInstruction::eContextWriteMemoryRandomBits:
|
|
case EmulateInstruction::eContextArithmetic:
|
|
case EmulateInstruction::eContextAdvancePC:
|
|
case EmulateInstruction::eContextReturnFromException:
|
|
case EmulateInstruction::eContextPopRegisterOffStack:
|
|
case EmulateInstruction::eContextAdjustStackPointer:
|
|
break;
|
|
|
|
case EmulateInstruction::eContextPushRegisterOnStack: {
|
|
uint32_t reg_num = LLDB_INVALID_REGNUM;
|
|
uint32_t generic_regnum = LLDB_INVALID_REGNUM;
|
|
assert(context.GetInfoType() ==
|
|
EmulateInstruction::eInfoTypeRegisterToRegisterPlusOffset &&
|
|
"unhandled case, add code to handle this!");
|
|
const uint32_t unwind_reg_kind = m_unwind_plan_ptr->GetRegisterKind();
|
|
reg_num = context.info.RegisterToRegisterPlusOffset.data_reg
|
|
.kinds[unwind_reg_kind];
|
|
generic_regnum = context.info.RegisterToRegisterPlusOffset.data_reg
|
|
.kinds[eRegisterKindGeneric];
|
|
|
|
if (reg_num != LLDB_INVALID_REGNUM &&
|
|
generic_regnum != LLDB_REGNUM_GENERIC_SP) {
|
|
if (m_pushed_regs.find(reg_num) == m_pushed_regs.end()) {
|
|
m_pushed_regs[reg_num] = addr;
|
|
const int32_t offset = addr - m_initial_sp;
|
|
m_curr_row->SetRegisterLocationToAtCFAPlusOffset(reg_num, offset,
|
|
/*can_replace=*/true);
|
|
m_curr_row_modified = true;
|
|
}
|
|
}
|
|
} break;
|
|
}
|
|
|
|
return dst_len;
|
|
}
|
|
|
|
bool UnwindAssemblyInstEmulation::ReadRegister(EmulateInstruction *instruction,
|
|
void *baton,
|
|
const RegisterInfo *reg_info,
|
|
RegisterValue ®_value) {
|
|
|
|
if (baton && reg_info)
|
|
return ((UnwindAssemblyInstEmulation *)baton)
|
|
->ReadRegister(instruction, reg_info, reg_value);
|
|
return false;
|
|
}
|
|
bool UnwindAssemblyInstEmulation::ReadRegister(EmulateInstruction *instruction,
|
|
const RegisterInfo *reg_info,
|
|
RegisterValue ®_value) {
|
|
bool synthetic = GetRegisterValue(*reg_info, reg_value);
|
|
|
|
Log *log = GetLog(LLDBLog::Unwind);
|
|
|
|
if (log && log->GetVerbose()) {
|
|
|
|
StreamString strm;
|
|
strm.Printf("UnwindAssemblyInstEmulation::ReadRegister (name = \"%s\") => "
|
|
"synthetic_value = %i, value = ",
|
|
reg_info->name, synthetic);
|
|
DumpRegisterValue(reg_value, strm, *reg_info, false, false, eFormatDefault);
|
|
log->PutString(strm.GetString());
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool UnwindAssemblyInstEmulation::WriteRegister(
|
|
EmulateInstruction *instruction, void *baton,
|
|
const EmulateInstruction::Context &context, const RegisterInfo *reg_info,
|
|
const RegisterValue ®_value) {
|
|
if (baton && reg_info)
|
|
return ((UnwindAssemblyInstEmulation *)baton)
|
|
->WriteRegister(instruction, context, reg_info, reg_value);
|
|
return false;
|
|
}
|
|
bool UnwindAssemblyInstEmulation::WriteRegister(
|
|
EmulateInstruction *instruction, const EmulateInstruction::Context &context,
|
|
const RegisterInfo *reg_info, const RegisterValue ®_value) {
|
|
Log *log = GetLog(LLDBLog::Unwind);
|
|
|
|
if (log && log->GetVerbose()) {
|
|
|
|
StreamString strm;
|
|
strm.Printf(
|
|
"UnwindAssemblyInstEmulation::WriteRegister (name = \"%s\", value = ",
|
|
reg_info->name);
|
|
DumpRegisterValue(reg_value, strm, *reg_info, false, false, eFormatDefault);
|
|
strm.PutCString(", context = ");
|
|
context.Dump(strm, instruction);
|
|
log->PutString(strm.GetString());
|
|
}
|
|
|
|
SetRegisterValue(*reg_info, reg_value);
|
|
|
|
switch (context.type) {
|
|
case EmulateInstruction::eContextInvalid:
|
|
case EmulateInstruction::eContextReadOpcode:
|
|
case EmulateInstruction::eContextImmediate:
|
|
case EmulateInstruction::eContextAdjustBaseRegister:
|
|
case EmulateInstruction::eContextRegisterPlusOffset:
|
|
case EmulateInstruction::eContextAdjustPC:
|
|
case EmulateInstruction::eContextRegisterStore:
|
|
case EmulateInstruction::eContextSupervisorCall:
|
|
case EmulateInstruction::eContextTableBranchReadMemory:
|
|
case EmulateInstruction::eContextWriteRegisterRandomBits:
|
|
case EmulateInstruction::eContextWriteMemoryRandomBits:
|
|
case EmulateInstruction::eContextAdvancePC:
|
|
case EmulateInstruction::eContextReturnFromException:
|
|
case EmulateInstruction::eContextPushRegisterOnStack:
|
|
case EmulateInstruction::eContextRegisterLoad:
|
|
// {
|
|
// const uint32_t reg_num =
|
|
// reg_info->kinds[m_unwind_plan_ptr->GetRegisterKind()];
|
|
// if (reg_num != LLDB_INVALID_REGNUM)
|
|
// {
|
|
// const bool can_replace_only_if_unspecified = true;
|
|
//
|
|
// m_curr_row.SetRegisterLocationToUndefined (reg_num,
|
|
// can_replace_only_if_unspecified,
|
|
// can_replace_only_if_unspecified);
|
|
// m_curr_row_modified = true;
|
|
// }
|
|
// }
|
|
break;
|
|
|
|
case EmulateInstruction::eContextArithmetic: {
|
|
// If we adjusted the current frame pointer by a constant then adjust the
|
|
// CFA offset
|
|
// with the same amount.
|
|
lldb::RegisterKind kind = m_unwind_plan_ptr->GetRegisterKind();
|
|
if (m_fp_is_cfa && reg_info->kinds[kind] == m_cfa_reg_info.kinds[kind] &&
|
|
context.GetInfoType() ==
|
|
EmulateInstruction::eInfoTypeRegisterPlusOffset &&
|
|
context.info.RegisterPlusOffset.reg.kinds[kind] ==
|
|
m_cfa_reg_info.kinds[kind]) {
|
|
const int64_t offset = context.info.RegisterPlusOffset.signed_offset;
|
|
m_curr_row->GetCFAValue().IncOffset(-1 * offset);
|
|
m_curr_row_modified = true;
|
|
}
|
|
} break;
|
|
|
|
case EmulateInstruction::eContextAbsoluteBranchRegister:
|
|
case EmulateInstruction::eContextRelativeBranchImmediate: {
|
|
if (context.GetInfoType() == EmulateInstruction::eInfoTypeISAAndImmediate &&
|
|
context.info.ISAAndImmediate.unsigned_data32 > 0) {
|
|
m_forward_branch_offset =
|
|
context.info.ISAAndImmediateSigned.signed_data32;
|
|
} else if (context.GetInfoType() ==
|
|
EmulateInstruction::eInfoTypeISAAndImmediateSigned &&
|
|
context.info.ISAAndImmediateSigned.signed_data32 > 0) {
|
|
m_forward_branch_offset = context.info.ISAAndImmediate.unsigned_data32;
|
|
} else if (context.GetInfoType() ==
|
|
EmulateInstruction::eInfoTypeImmediate &&
|
|
context.info.unsigned_immediate > 0) {
|
|
m_forward_branch_offset = context.info.unsigned_immediate;
|
|
} else if (context.GetInfoType() ==
|
|
EmulateInstruction::eInfoTypeImmediateSigned &&
|
|
context.info.signed_immediate > 0) {
|
|
m_forward_branch_offset = context.info.signed_immediate;
|
|
}
|
|
} break;
|
|
|
|
case EmulateInstruction::eContextPopRegisterOffStack: {
|
|
const uint32_t reg_num =
|
|
reg_info->kinds[m_unwind_plan_ptr->GetRegisterKind()];
|
|
const uint32_t generic_regnum = reg_info->kinds[eRegisterKindGeneric];
|
|
if (reg_num != LLDB_INVALID_REGNUM &&
|
|
generic_regnum != LLDB_REGNUM_GENERIC_SP) {
|
|
switch (context.GetInfoType()) {
|
|
case EmulateInstruction::eInfoTypeAddress:
|
|
if (m_pushed_regs.find(reg_num) != m_pushed_regs.end() &&
|
|
context.info.address == m_pushed_regs[reg_num]) {
|
|
m_curr_row->SetRegisterLocationToSame(reg_num,
|
|
false /*must_replace*/);
|
|
m_curr_row_modified = true;
|
|
|
|
// FP has been restored to its original value, we are back
|
|
// to using SP to calculate the CFA.
|
|
if (m_fp_is_cfa) {
|
|
m_fp_is_cfa = false;
|
|
lldb::RegisterKind sp_reg_kind = eRegisterKindGeneric;
|
|
uint32_t sp_reg_num = LLDB_REGNUM_GENERIC_SP;
|
|
RegisterInfo sp_reg_info =
|
|
*m_inst_emulator_up->GetRegisterInfo(sp_reg_kind, sp_reg_num);
|
|
RegisterValue sp_reg_val;
|
|
if (GetRegisterValue(sp_reg_info, sp_reg_val)) {
|
|
m_cfa_reg_info = sp_reg_info;
|
|
const uint32_t cfa_reg_num =
|
|
sp_reg_info.kinds[m_unwind_plan_ptr->GetRegisterKind()];
|
|
assert(cfa_reg_num != LLDB_INVALID_REGNUM);
|
|
m_curr_row->GetCFAValue().SetIsRegisterPlusOffset(
|
|
cfa_reg_num, m_initial_sp - sp_reg_val.GetAsUInt64());
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case EmulateInstruction::eInfoTypeISA:
|
|
assert(
|
|
(generic_regnum == LLDB_REGNUM_GENERIC_PC ||
|
|
generic_regnum == LLDB_REGNUM_GENERIC_FLAGS) &&
|
|
"eInfoTypeISA used for popping a register other the PC/FLAGS");
|
|
if (generic_regnum != LLDB_REGNUM_GENERIC_FLAGS) {
|
|
m_curr_row->SetRegisterLocationToSame(reg_num,
|
|
false /*must_replace*/);
|
|
m_curr_row_modified = true;
|
|
}
|
|
break;
|
|
default:
|
|
assert(false && "unhandled case, add code to handle this!");
|
|
break;
|
|
}
|
|
}
|
|
} break;
|
|
|
|
case EmulateInstruction::eContextSetFramePointer:
|
|
if (!m_fp_is_cfa) {
|
|
m_fp_is_cfa = true;
|
|
m_cfa_reg_info = *reg_info;
|
|
const uint32_t cfa_reg_num =
|
|
reg_info->kinds[m_unwind_plan_ptr->GetRegisterKind()];
|
|
assert(cfa_reg_num != LLDB_INVALID_REGNUM);
|
|
m_curr_row->GetCFAValue().SetIsRegisterPlusOffset(
|
|
cfa_reg_num, m_initial_sp - reg_value.GetAsUInt64());
|
|
m_curr_row_modified = true;
|
|
}
|
|
break;
|
|
|
|
case EmulateInstruction::eContextRestoreStackPointer:
|
|
if (m_fp_is_cfa) {
|
|
m_fp_is_cfa = false;
|
|
m_cfa_reg_info = *reg_info;
|
|
const uint32_t cfa_reg_num =
|
|
reg_info->kinds[m_unwind_plan_ptr->GetRegisterKind()];
|
|
assert(cfa_reg_num != LLDB_INVALID_REGNUM);
|
|
m_curr_row->GetCFAValue().SetIsRegisterPlusOffset(
|
|
cfa_reg_num, m_initial_sp - reg_value.GetAsUInt64());
|
|
m_curr_row_modified = true;
|
|
}
|
|
break;
|
|
|
|
case EmulateInstruction::eContextAdjustStackPointer:
|
|
// If we have created a frame using the frame pointer, don't follow
|
|
// subsequent adjustments to the stack pointer.
|
|
if (!m_fp_is_cfa) {
|
|
m_curr_row->GetCFAValue().SetIsRegisterPlusOffset(
|
|
m_curr_row->GetCFAValue().GetRegisterNumber(),
|
|
m_initial_sp - reg_value.GetAsUInt64());
|
|
m_curr_row_modified = true;
|
|
}
|
|
break;
|
|
}
|
|
return true;
|
|
}
|