f8d40181c9
In PPCBoolRetToInt bool value is changed to i32 type. On ppc64 it may introduce an extra zero extension for the return value. This patch changes the integer type to i64 to avoid the zero extension on ppc64. This patch fixed PR32442. Differential Revision: https://reviews.llvm.org/D31407 llvm-svn: 298955
447 lines
15 KiB
C++
447 lines
15 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "PPC.h"
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#include "PPCSubtarget.h"
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#include "PPCTargetObjectFile.h"
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#include "PPCTargetMachine.h"
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#include "PPCTargetTransformInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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#include <cassert>
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#include <memory>
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#include <string>
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using namespace llvm;
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static cl::
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opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
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cl::desc("Disable CTR loops for PPC"));
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static cl::
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opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
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cl::desc("Disable PPC loop preinc prep"));
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static cl::opt<bool>
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VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
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cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
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static cl::
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opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
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cl::desc("Disable VSX Swap Removal for PPC"));
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static cl::
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opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
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cl::desc("Disable QPX load splat simplification"));
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static cl::
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opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
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cl::desc("Disable machine peepholes for PPC"));
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static cl::opt<bool>
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EnableGEPOpt("ppc-gep-opt", cl::Hidden,
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cl::desc("Enable optimizations on complex GEPs"),
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cl::init(true));
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static cl::opt<bool>
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EnablePrefetch("enable-ppc-prefetching",
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cl::desc("disable software prefetching on PPC"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
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cl::desc("Add extra TOC register dependencies"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableMachineCombinerPass("ppc-machine-combiner",
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cl::desc("Enable the machine combiner pass"),
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cl::init(true), cl::Hidden);
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(getThePPC32Target());
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RegisterTargetMachine<PPC64TargetMachine> B(getThePPC64Target());
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RegisterTargetMachine<PPC64TargetMachine> C(getThePPC64LETarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializePPCBoolRetToIntPass(PR);
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initializePPCExpandISELPass(PR);
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}
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/// Return the datalayout string of a subtarget.
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static std::string getDataLayoutString(const Triple &T) {
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bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
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std::string Ret;
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// Most PPC* platforms are big endian, PPC64LE is little endian.
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if (T.getArch() == Triple::ppc64le)
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Ret = "e";
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else
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Ret = "E";
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Ret += DataLayout::getManglingComponent(T);
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// PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
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// pointers.
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if (!is64Bit || T.getOS() == Triple::Lv2)
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Ret += "-p:32:32";
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// Note, the alignment values for f64 and i64 on ppc64 in Darwin
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// documentation are wrong; these are correct (i.e. "what gcc does").
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if (is64Bit || !T.isOSDarwin())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
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if (is64Bit)
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Ret += "-n32:64";
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else
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Ret += "-n32";
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return Ret;
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}
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static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
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const Triple &TT) {
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std::string FullFS = FS;
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// Make sure 64-bit features are available when CPUname is generic
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if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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}
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if (OL >= CodeGenOpt::Default) {
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if (!FullFS.empty())
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FullFS = "+crbits," + FullFS;
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else
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FullFS = "+crbits";
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}
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if (OL != CodeGenOpt::None) {
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if (!FullFS.empty())
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FullFS = "+invariant-function-descriptors," + FullFS;
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else
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FullFS = "+invariant-function-descriptors";
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}
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return FullFS;
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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// If it isn't a Mach-O file then it's going to be a linux ELF
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// object file.
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if (TT.isOSDarwin())
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return llvm::make_unique<TargetLoweringObjectFileMachO>();
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return llvm::make_unique<PPC64LinuxTargetObjectFile>();
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}
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static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
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const TargetOptions &Options) {
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if (Options.MCOptions.getABIName().startswith("elfv1"))
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return PPCTargetMachine::PPC_ABI_ELFv1;
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else if (Options.MCOptions.getABIName().startswith("elfv2"))
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return PPCTargetMachine::PPC_ABI_ELFv2;
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assert(Options.MCOptions.getABIName().empty() &&
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"Unknown target-abi option!");
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if (!TT.isMacOSX()) {
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switch (TT.getArch()) {
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case Triple::ppc64le:
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return PPCTargetMachine::PPC_ABI_ELFv2;
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case Triple::ppc64:
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return PPCTargetMachine::PPC_ABI_ELFv1;
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default:
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// Fallthrough.
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;
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}
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}
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return PPCTargetMachine::PPC_ABI_UNKNOWN;
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue()) {
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if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
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if (!TT.isOSBinFormatMachO() && !TT.isMacOSX())
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return Reloc::PIC_;
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}
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if (TT.isOSDarwin())
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return Reloc::DynamicNoPIC;
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return Reloc::Static;
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}
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return *RM;
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}
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// The FeatureString here is a little subtle. We are modifying the feature
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// string with what are (currently) non-function specific overrides as it goes
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// into the LLVMTargetMachine constructor and then using the stored value in the
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// Subtarget constructor below it.
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PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM, CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
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computeFSAdditions(FS, OL, TT), Options,
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getEffectiveRelocModel(TT, RM), CM, OL),
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TLOF(createTLOF(getTargetTriple())),
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TargetABI(computeTargetABI(TT, Options)),
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Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) {
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initAsmInfo();
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}
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PPCTargetMachine::~PPCTargetMachine() = default;
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void PPC32TargetMachine::anchor() {}
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
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void PPC64TargetMachine::anchor() {}
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
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const PPCSubtarget *
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PPCTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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bool SoftFloat =
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F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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// If the soft float attribute is set on the function turn on the soft float
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// subtarget feature.
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if (SoftFloat)
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FS += FS.empty() ? "-hard-float" : ",-hard-float";
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<PPCSubtarget>(
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TargetTriple, CPU,
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// FIXME: It would be good to have the subtarget additions here
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// not necessary. Anything that turns them on/off (overrides) ends
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// up being put at the end of the feature string, but the defaults
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// shouldn't require adding them. Fixing this means pulling Feature64Bit
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// out of most of the target cpus in the .td file and making it set only
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// as part of initialization via the TargetTriple.
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computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
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}
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return I.get();
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// PPC Code Generator Pass Configuration Options.
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class PPCPassConfig : public TargetPassConfig {
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public:
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PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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PPCTargetMachine &getPPCTargetMachine() const {
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return getTM<PPCTargetMachine>();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addILPOpts() override;
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bool addInstSelector() override;
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void addMachineSSAOptimization() override;
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // end anonymous namespace
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TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new PPCPassConfig(this, PM);
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}
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void PPCPassConfig::addIRPasses() {
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createPPCBoolRetToIntPass(&getPPCTargetMachine()));
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addPass(createAtomicExpandPass(&getPPCTargetMachine()));
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// For the BG/Q (or if explicitly requested), add explicit data prefetch
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// intrinsics.
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bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
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getOptLevel() != CodeGenOpt::None;
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if (EnablePrefetch.getNumOccurrences() > 0)
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UsePrefetching = EnablePrefetch;
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if (UsePrefetching)
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addPass(createLoopDataPrefetchPass());
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if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
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// Call SeparateConstOffsetFromGEP pass to extract constants within indices
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// and lower a GEP with multiple indices to either arithmetic operations or
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// multiple GEPs with single index.
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addPass(createSeparateConstOffsetFromGEPPass(TM, true));
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// Call EarlyCSE pass to find and remove subexpressions in the lowered
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// result.
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addPass(createEarlyCSEPass());
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// Do loop invariant code motion in case part of the lowered result is
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// invariant.
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addPass(createLICMPass());
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}
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TargetPassConfig::addIRPasses();
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}
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bool PPCPassConfig::addPreISel() {
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if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCCTRLoops(getPPCTargetMachine()));
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return false;
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}
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bool PPCPassConfig::addILPOpts() {
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addPass(&EarlyIfConverterID);
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if (EnableMachineCombinerPass)
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addPass(&MachineCombinerID);
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return true;
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}
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bool PPCPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createPPCISelDag(getPPCTargetMachine()));
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#ifndef NDEBUG
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCCTRLoopsVerify());
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#endif
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addPass(createPPCVSXCopyPass());
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return false;
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}
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void PPCPassConfig::addMachineSSAOptimization() {
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TargetPassConfig::addMachineSSAOptimization();
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// For little endian, remove where possible the vector swap instructions
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// introduced at code generation to normalize vector element order.
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if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
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!DisableVSXSwapRemoval)
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addPass(createPPCVSXSwapRemovalPass());
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// Target-specific peephole cleanups performed after instruction
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// selection.
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if (!DisableMIPeephole) {
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addPass(createPPCMIPeepholePass());
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addPass(&DeadMachineInstructionElimID);
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}
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}
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void PPCPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
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insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
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&PPCVSXFMAMutateID);
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}
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// FIXME: We probably don't need to run these for -fPIE.
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if (getPPCTargetMachine().isPositionIndependent()) {
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// FIXME: LiveVariables should not be necessary here!
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// PPCTLSDYnamicCallPass uses LiveIntervals which previously dependet on
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// LiveVariables. This (unnecessary) dependency has been removed now,
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// however a stage-2 clang build fails without LiveVariables computed here.
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addPass(&LiveVariablesID, false);
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addPass(createPPCTLSDynamicCallPass());
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}
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if (EnableExtraTOCRegDeps)
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addPass(createPPCTOCRegDepsPass());
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}
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void PPCPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(&IfConverterID);
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// This optimization must happen after anything that might do store-to-load
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// forwarding. Here we're after RA (and, thus, when spills are inserted)
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// but before post-RA scheduling.
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if (!DisableQPXLoadSplat)
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addPass(createPPCQPXLoadSplatPass());
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}
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}
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void PPCPassConfig::addPreEmitPass() {
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addPass(createPPCExpandISELPass());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createPPCEarlyReturnPass(), false);
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// Must run branch selection immediately preceding the asm printer.
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addPass(createPPCBranchSelectionPass(), false);
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}
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TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis([this](const Function &F) {
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return TargetTransformInfo(PPCTTIImpl(this, F));
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});
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}
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