Craig Topper 13fe673301 [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. ...

Rather than having a separate pass to add the hint instructions,
emit them directly into the streamer during asm printing.

Reviewed By: BeMg, kito-cheng

Differential Revision: https://reviews.llvm.org/D149511

2023-05-01 12:05:18 -07:00

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Analysis

[ValueTracking] Add additional cases for isKnownNonZero(mul X, Y)

2023-04-30 10:06:46 -05:00

Assembler

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Bindings

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Bitcode

[ThinLTO] Remove BlockCount for non partial sample profile builds

2023-04-20 11:45:15 -07:00

BugPoint

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CodeGen

[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.

2023-05-01 12:05:18 -07:00

DebugInfo

[Assignment Tracking] Check getTypeSizeInBits result for scalable vector types

2023-04-28 09:10:38 +01:00

Demangle

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Examples

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ExecutionEngine

[JITLink][AArch64] Implement R_AARCH64_CONDBR19

2023-04-26 10:22:36 +02:00

Feature

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FileCheck

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Instrumentation

[test][HWASAN] Auto-generate a few tests

2023-04-30 22:06:52 -07:00

Integer

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JitListener

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Linker

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LTO

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MachineVerifier

[X86] Fix checks for illegal physreg COPY instructions

2023-04-18 12:03:06 +01:00

MC

MC: Use parseEOL

2023-04-28 00:52:33 -07:00

Object

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ObjectYAML

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Other

Reapply Move "auto-init" instructions to the dominator of their users

2023-04-24 18:10:10 +02:00

SafepointIRVerifier

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Support

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SymbolRewriter

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TableGen

TableGen: Let expressions available to list subscriptions and list slices

2023-04-26 23:47:16 +09:00

ThinLTO/X86

Restore "[MemProf] Context disambiguation cloning pass [patch 2/3]"

2023-04-21 19:38:46 -07:00

tools

[llvm-profdata] Deprecate Compact Binary Sample Profile Format

2023-05-01 17:10:08 +00:00

Transforms

Revert "[ValueTracking] Use knownbits interface for determining if div/rem are safe to speculate"

2023-05-01 13:20:09 -05:00

Unit

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Verifier

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YAMLParser

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.clang-format

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CMakeLists.txt

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lit.cfg.py

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lit.site.cfg.py.in

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TestRunner.sh

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