262c2c0fd2
vectorize-buffer-fat-pointer.ll required a manual check line fix. vector-alloca-addrspacecast.ll required a manual fixup of a check line. partial-regcopy-and-spill-missed-at-regalloc.ll required re-running update_mir_test_checks. The HSA metadata tests required avoiding the script touching the type name in the metadata. annotate-noclobber.ll ran into one update script bug. It deleted a check line with a 0 offset GEP, moving the following -NEXT check logically up one line.
93 lines
3.6 KiB
LLVM
93 lines
3.6 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefixes=PAL,CI --enable-var-scope %s
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; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefixes=PAL,VI --enable-var-scope %s
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; PAL-NOT: .AMDGPU.config
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; PAL-LABEL: {{^}}simple:
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define amdgpu_kernel void @simple(ptr addrspace(1) %out) {
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entry:
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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; Check code sequence for amdpal use of scratch for alloca. This is the case
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; where the high half of the address comes from s_getpc.
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; PAL-LABEL: {{^}}scratch:
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; PAL: s_getpc_b64 s[[[GITPTR:[0-9]+]]:
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; PAL: s_mov_b32 s[[GITPTR]], s0
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; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:
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; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
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define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, ptr addrspace(5) %out) {
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entry:
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%v = alloca [2 x i32], addrspace(5)
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store <2 x i32> %in, ptr addrspace(5) %v
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%e = getelementptr [2 x i32], ptr addrspace(5) %v, i32 0, i32 %idx
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%x = load i32, ptr addrspace(5) %e
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store i32 %x, ptr addrspace(5) %out
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ret void
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}
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; Check code sequence for amdpal use of scratch for alloca. This is the case
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; where the amdgpu-git-ptr-high function attribute gives the high half of the
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; address to use.
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; Looks like you can't do arithmetic on a filecheck variable, so we can't test
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; that the s_movk_i32 is into a reg that is one more than the following
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; s_mov_b32.
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; PAL-LABEL: {{^}}scratch2:
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; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
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; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
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; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:
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; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
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define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, ptr addrspace(5) %out) #0 {
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entry:
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%v = alloca [2 x i32], addrspace(5)
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store <2 x i32> %in, ptr addrspace(5) %v
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%e = getelementptr [2 x i32], ptr addrspace(5) %v, i32 0, i32 %idx
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%x = load i32, ptr addrspace(5) %e
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store i32 %x, ptr addrspace(5) %out
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ret void
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}
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; Check code sequence for amdpal use of scratch for alloca in a compute shader.
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; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
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; 0 in a graphics shader.
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; Prior to GCN3 s_load_dword offsets are dwords, so the offset will be 0x4.
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; PAL-LABEL: {{^}}scratch2_cs:
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; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
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; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
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; CI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x4
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; VI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x10
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; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
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define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
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entry:
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%v = alloca [3 x i32], addrspace(5)
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%v1 = getelementptr [3 x i32], ptr addrspace(5) %v, i32 0, i32 1
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store i32 %extra, ptr addrspace(5) %v
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store <2 x i32> %in, ptr addrspace(5) %v1
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%e = getelementptr [2 x i32], ptr addrspace(5) %v1, i32 0, i32 %idx
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%x = load i32, ptr addrspace(5) %e
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%xf = bitcast i32 %x to float
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call void @llvm.amdgcn.raw.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i32 0)
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ret void
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}
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attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
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declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg)
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; PAL: .amdgpu_pal_metadata
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; PAL-NEXT: ---
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; PAL-NEXT: amdpal.pipelines:
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; PAL-NEXT: - .hardware_stages:
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; PAL-NEXT: .cs:
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; PAL-NEXT: .entry_point: scratch2_cs
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; PAL-NEXT: .scratch_memory_size: 0x10
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; PAL-NEXT: .sgpr_count: 0x
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; PAL-NEXT: .vgpr_count: 0x
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