09fe84abb4
Moving code sinking pass before structurizer creates more sinking opportunities. The extra flow edges introduced by the structurizer can have adverse effects on sinking, because the sinking pass prefers moving instructions to blocks with unique predecessors and the structurizer destroys that property in some cases. A notable example is moving high-latency image instructions across kills. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D101115
92 lines
2.9 KiB
LLVM
92 lines
2.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Where the mask of lanes wanting to exit the loop on this iteration is not
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; obviously already masked by exec (in this case, the xor with -1 inserted by
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; control flow annotation), then lower control flow must insert an S_AND_B64
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; with exec.
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; GCN-LABEL: {{^}}needs_and:
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; GCN: s_or_b64 exec, exec, [[REG1:[^ ,]*]]
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; GCN: s_andn2_b64 exec, exec, [[REG2:[^ ,]*]]
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; GCN: s_or_b64 [[REG2:[^ ,]*]], [[REG1:[^ ,]*]], [[REG2:[^ ,]*]]
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; GCN: s_or_b64 exec, exec, [[REG2:[^ ,]*]]
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define void @needs_and(i32 %arg) {
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entry:
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br label %loop
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loop:
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%tmp23phi = phi i32 [ %tmp23, %endif ], [ 0, %entry ]
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%tmp23 = add nuw i32 %tmp23phi, 1
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%tmp27 = icmp ult i32 %arg, %tmp23
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br i1 %tmp27, label %then, label %endif
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then: ; preds = %bb
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call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i32 0)
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br label %endif
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endif: ; preds = %bb28, %bb
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br i1 %tmp27, label %loop, label %loopexit
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loopexit:
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ret void
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}
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; Where the mask of lanes wanting to exit the loop on this iteration is
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; obviously already masked by exec (a V_CMP), then lower control flow can omit
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; the S_AND_B64 to avoid an unnecessary instruction.
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; GCN-LABEL: {{^}}doesnt_need_and:
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; GCN: v_cmp{{[^ ]*}} [[REG1:[^ ,]*]]
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; GCN: s_or_b64 [[REG2:[^ ,]*]], [[REG1]],
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; GCN: s_andn2_b64 exec, exec, [[REG2]]
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define void @doesnt_need_and(i32 %arg) {
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entry:
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br label %loop
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loop:
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%tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ]
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%tmp23 = add nuw i32 %tmp23phi, 1
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%tmp27 = icmp ult i32 %arg, %tmp23
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call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i32 0)
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br i1 %tmp27, label %loop, label %loopexit
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loopexit:
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ret void
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}
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; Another case where the mask of lanes wanting to exit the loop is not masked
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; by exec, because it is a function parameter.
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; GCN-LABEL: {{^}}break_cond_is_arg:
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; GCN: s_xor_b64 [[REG1:[^ ,]*]], {{[^ ,]*, -1$}}
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; GCN: s_andn2_b64 exec, exec, [[REG3:[^ ,]*]]
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; GCN: s_and_b64 [[REG2:[^ ,]*]], exec, [[REG1]]
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; GCN: s_or_b64 [[REG3]], [[REG2]],
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define void @break_cond_is_arg(i32 %arg, i1 %breakcond) {
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entry:
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br label %loop
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loop:
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%tmp23phi = phi i32 [ %tmp23, %endif ], [ 0, %entry ]
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%tmp23 = add nuw i32 %tmp23phi, 1
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%tmp27 = icmp ult i32 %arg, %tmp23
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br i1 %tmp27, label %then, label %endif
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then: ; preds = %bb
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call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i32 0)
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br label %endif
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endif: ; preds = %bb28, %bb
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br i1 %breakcond, label %loop, label %loopexit
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loopexit:
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ret void
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}
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declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
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attributes #0 = { nounwind writeonly }
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