54cf69c9d5
Summary: This patch introduces a mechanism to check the code object version from the module flag, This avoids checking from command line. In case the module flag is missing, we use the current default code object version supported in the compiler. For tools whose inputs are not IR, we may need other approach (directive, for example) to check the code object version, That will be in a separate patch later. For LIT tests update, we directly add module flag if there is only a single code object version associated with all checks in one file. In cause of multiple code object version in one file, we use the "sed" method to "clone" the checks to achieve the goal. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D14313
321 lines
14 KiB
LLVM
321 lines
14 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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; Make sure the stack is never realigned for entry functions.
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define amdgpu_kernel void @max_alignment_128() #0 {
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; VI-LABEL: max_alignment_128:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_u32 s0, s0, s7
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; VI-NEXT: s_addc_u32 s1, s1, 0
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; VI-NEXT: v_mov_b32_e32 v0, 9
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_endpgm
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; VI-NEXT: .section .rodata,#alloc
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; VI-NEXT: .p2align 6
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; VI-NEXT: .amdhsa_kernel max_alignment_128
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; VI-NEXT: .amdhsa_group_segment_fixed_size 0
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; VI-NEXT: .amdhsa_private_segment_fixed_size 256
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; VI-NEXT: .amdhsa_kernarg_size 0
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; VI-NEXT: .amdhsa_user_sgpr_count 6
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; VI-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; VI-NEXT: .amdhsa_next_free_vgpr 1
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; VI-NEXT: .amdhsa_next_free_sgpr 8
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; VI-NEXT: .amdhsa_reserve_vcc 0
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; VI-NEXT: .amdhsa_reserve_flat_scratch 0
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; VI-NEXT: .amdhsa_float_round_mode_32 0
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; VI-NEXT: .amdhsa_float_round_mode_16_64 0
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; VI-NEXT: .amdhsa_float_denorm_mode_32 3
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; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; VI-NEXT: .amdhsa_dx10_clamp 1
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; VI-NEXT: .amdhsa_ieee_mode 1
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; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; VI-NEXT: .amdhsa_exception_fp_denorm_src 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; VI-NEXT: .amdhsa_exception_int_div_zero 0
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; VI-NEXT: .end_amdhsa_kernel
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; VI-NEXT: .text
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;
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; GFX9-LABEL: max_alignment_128:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 s0, s0, s7
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: v_mov_b32_e32 v0, 9
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .section .rodata,#alloc
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; GFX9-NEXT: .p2align 6
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; GFX9-NEXT: .amdhsa_kernel max_alignment_128
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; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
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; GFX9-NEXT: .amdhsa_private_segment_fixed_size 256
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; GFX9-NEXT: .amdhsa_kernarg_size 0
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; GFX9-NEXT: .amdhsa_user_sgpr_count 6
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GFX9-NEXT: .amdhsa_next_free_vgpr 1
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; GFX9-NEXT: .amdhsa_next_free_sgpr 8
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; GFX9-NEXT: .amdhsa_reserve_vcc 0
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; GFX9-NEXT: .amdhsa_reserve_flat_scratch 0
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; GFX9-NEXT: .amdhsa_reserve_xnack_mask 1
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; GFX9-NEXT: .amdhsa_float_round_mode_32 0
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; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_32 3
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; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; GFX9-NEXT: .amdhsa_dx10_clamp 1
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; GFX9-NEXT: .amdhsa_ieee_mode 1
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; GFX9-NEXT: .amdhsa_fp16_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; GFX9-NEXT: .amdhsa_exception_int_div_zero 0
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; GFX9-NEXT: .end_amdhsa_kernel
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; GFX9-NEXT: .text
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%alloca.align = alloca i32, align 128, addrspace(5)
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store volatile i32 9, ptr addrspace(5) %alloca.align, align 128
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ret void
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}
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define amdgpu_kernel void @stackrealign_attr() #1 {
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; VI-LABEL: stackrealign_attr:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_u32 s0, s0, s7
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; VI-NEXT: s_addc_u32 s1, s1, 0
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; VI-NEXT: v_mov_b32_e32 v0, 9
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_endpgm
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; VI-NEXT: .section .rodata,#alloc
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; VI-NEXT: .p2align 6
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; VI-NEXT: .amdhsa_kernel stackrealign_attr
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; VI-NEXT: .amdhsa_group_segment_fixed_size 0
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; VI-NEXT: .amdhsa_private_segment_fixed_size 8
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; VI-NEXT: .amdhsa_kernarg_size 0
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; VI-NEXT: .amdhsa_user_sgpr_count 6
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; VI-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; VI-NEXT: .amdhsa_next_free_vgpr 1
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; VI-NEXT: .amdhsa_next_free_sgpr 8
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; VI-NEXT: .amdhsa_reserve_vcc 0
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; VI-NEXT: .amdhsa_reserve_flat_scratch 0
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; VI-NEXT: .amdhsa_float_round_mode_32 0
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; VI-NEXT: .amdhsa_float_round_mode_16_64 0
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; VI-NEXT: .amdhsa_float_denorm_mode_32 3
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; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; VI-NEXT: .amdhsa_dx10_clamp 1
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; VI-NEXT: .amdhsa_ieee_mode 1
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; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; VI-NEXT: .amdhsa_exception_fp_denorm_src 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; VI-NEXT: .amdhsa_exception_int_div_zero 0
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; VI-NEXT: .end_amdhsa_kernel
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; VI-NEXT: .text
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;
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; GFX9-LABEL: stackrealign_attr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 s0, s0, s7
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: v_mov_b32_e32 v0, 9
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .section .rodata,#alloc
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; GFX9-NEXT: .p2align 6
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; GFX9-NEXT: .amdhsa_kernel stackrealign_attr
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; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
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; GFX9-NEXT: .amdhsa_private_segment_fixed_size 8
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; GFX9-NEXT: .amdhsa_kernarg_size 0
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; GFX9-NEXT: .amdhsa_user_sgpr_count 6
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GFX9-NEXT: .amdhsa_next_free_vgpr 1
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; GFX9-NEXT: .amdhsa_next_free_sgpr 8
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; GFX9-NEXT: .amdhsa_reserve_vcc 0
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; GFX9-NEXT: .amdhsa_reserve_flat_scratch 0
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; GFX9-NEXT: .amdhsa_reserve_xnack_mask 1
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; GFX9-NEXT: .amdhsa_float_round_mode_32 0
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; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_32 3
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; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; GFX9-NEXT: .amdhsa_dx10_clamp 1
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; GFX9-NEXT: .amdhsa_ieee_mode 1
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; GFX9-NEXT: .amdhsa_fp16_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; GFX9-NEXT: .amdhsa_exception_int_div_zero 0
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; GFX9-NEXT: .end_amdhsa_kernel
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; GFX9-NEXT: .text
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%alloca.align = alloca i32, align 4, addrspace(5)
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store volatile i32 9, ptr addrspace(5) %alloca.align, align 4
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ret void
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}
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define amdgpu_kernel void @alignstack_attr() #2 {
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; VI-LABEL: alignstack_attr:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_u32 s0, s0, s7
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; VI-NEXT: s_addc_u32 s1, s1, 0
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; VI-NEXT: v_mov_b32_e32 v0, 9
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_endpgm
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; VI-NEXT: .section .rodata,#alloc
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; VI-NEXT: .p2align 6
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; VI-NEXT: .amdhsa_kernel alignstack_attr
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; VI-NEXT: .amdhsa_group_segment_fixed_size 0
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; VI-NEXT: .amdhsa_private_segment_fixed_size 128
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; VI-NEXT: .amdhsa_kernarg_size 0
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; VI-NEXT: .amdhsa_user_sgpr_count 6
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; VI-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; VI-NEXT: .amdhsa_next_free_vgpr 1
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; VI-NEXT: .amdhsa_next_free_sgpr 8
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; VI-NEXT: .amdhsa_reserve_vcc 0
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; VI-NEXT: .amdhsa_reserve_flat_scratch 0
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; VI-NEXT: .amdhsa_float_round_mode_32 0
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; VI-NEXT: .amdhsa_float_round_mode_16_64 0
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; VI-NEXT: .amdhsa_float_denorm_mode_32 3
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; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; VI-NEXT: .amdhsa_dx10_clamp 1
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; VI-NEXT: .amdhsa_ieee_mode 1
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; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; VI-NEXT: .amdhsa_exception_fp_denorm_src 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; VI-NEXT: .amdhsa_exception_int_div_zero 0
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; VI-NEXT: .end_amdhsa_kernel
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; VI-NEXT: .text
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;
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; GFX9-LABEL: alignstack_attr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 s0, s0, s7
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: v_mov_b32_e32 v0, 9
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .section .rodata,#alloc
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; GFX9-NEXT: .p2align 6
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; GFX9-NEXT: .amdhsa_kernel alignstack_attr
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; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
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; GFX9-NEXT: .amdhsa_private_segment_fixed_size 128
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; GFX9-NEXT: .amdhsa_kernarg_size 0
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; GFX9-NEXT: .amdhsa_user_sgpr_count 6
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GFX9-NEXT: .amdhsa_next_free_vgpr 1
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; GFX9-NEXT: .amdhsa_next_free_sgpr 8
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; GFX9-NEXT: .amdhsa_reserve_vcc 0
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; GFX9-NEXT: .amdhsa_reserve_flat_scratch 0
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; GFX9-NEXT: .amdhsa_reserve_xnack_mask 1
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; GFX9-NEXT: .amdhsa_float_round_mode_32 0
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; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_32 3
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; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; GFX9-NEXT: .amdhsa_dx10_clamp 1
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; GFX9-NEXT: .amdhsa_ieee_mode 1
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; GFX9-NEXT: .amdhsa_fp16_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0
|
|
; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0
|
|
; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0
|
|
; GFX9-NEXT: .amdhsa_exception_int_div_zero 0
|
|
; GFX9-NEXT: .end_amdhsa_kernel
|
|
; GFX9-NEXT: .text
|
|
%alloca.align = alloca i32, align 4, addrspace(5)
|
|
store volatile i32 9, ptr addrspace(5) %alloca.align, align 4
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind "stackrealign" }
|
|
attributes #2 = { nounwind alignstack=128 }
|
|
|
|
!llvm.module.flags = !{!0}
|
|
!0 = !{i32 1, !"amdgpu_code_object_version", i32 300}
|