cf40b8a4dd
We've a argument lowering logic to prevent floating-point value pass
passed with bit-conversion, but that rule should not applied to vector
arguments.
---
How to pass argument to `foo`:
```
tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer)
```
`foo` take 13 arguments, first 8 argument pass in GPR, and next 2 LMUL 8 vector
arguments passed in v8-v23, and now we run out of argument register for GPR and
vector register, so we must pass last LMUL 8 vector argument by stack.
Which means we should reserve `vlenb * 8` byte for stack for the last
vector argument.
Reviewed By: craig.topper, asb
Differential Revision: https://reviews.llvm.org/D145938
48 lines
1.8 KiB
LLVM
48 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s 2>&1 | FileCheck %s
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; CHECK-NOT: warning: Invalid size request on a scalable vector
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define void @bar() nounwind {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -96
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; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
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; CHECK-NEXT: addi s0, sp, 96
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: andi sp, sp, -64
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; CHECK-NEXT: mv s1, sp
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: addi a0, s1, 64
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: sd a0, 0(sp)
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: li a1, 0
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: li a3, 0
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; CHECK-NEXT: li a4, 0
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; CHECK-NEXT: li a5, 0
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; CHECK-NEXT: li a6, 0
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; CHECK-NEXT: li a7, 0
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; CHECK-NEXT: vmv.v.i v16, 0
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; CHECK-NEXT: call foo@plt
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: addi sp, s0, -96
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; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 96
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; CHECK-NEXT: ret
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entry:
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tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, <vscale x 16 x float> zeroinitializer, <vscale x 16 x float> zeroinitializer, <vscale x 16 x float> zeroinitializer)
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ret void
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}
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declare void @foo(i32, i32, i32, i32, i32, i32, i32, i32, <vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>) nounwind
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