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clang-p2996/llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
Carl Ritson ea9d6392f4 Fix reordering of instructions during VirtRegRewriter unbundling 
When unbundling COPY bundles in VirtRegRewriter the start of the
bundle is not correctly referenced in the unbundling loop.

The effect of this is that unbundled instructions are sometimes
inserted out-of-order, particular in cases where multiple
reordering have been applied to avoid clobbering dependencies.
The resulting instruction sequence clobbers dependencies.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D88821
2020-10-06 09:43:02 +09:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=greedy -o - -verify-machineinstrs %s | FileCheck -check-prefix=RA %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=greedy,virtregrewriter,post-RA-sched -o - -verify-machineinstrs %s | FileCheck -check-prefix=VR %s
---
name: splitkit_copy_bundle
tracksRegLiveness: true
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
body: |
; RA-LABEL: name: splitkit_copy_bundle
; RA: bb.0:
; RA: successors: %bb.1(0x80000000)
; RA: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; RA: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; RA: undef %5.sub1:sgpr_1024 = S_MOV_B32 -1
; RA: %5.sub0:sgpr_1024 = S_MOV_B32 -1
; RA: undef %4.sub0_sub1:sgpr_1024 = COPY %5.sub0_sub1
; RA: undef %3.sub0:sgpr_1024 = S_MOV_B32 0
; RA: bb.1:
; RA: successors: %bb.2(0x80000000)
; RA: undef %6.sub0_sub1:sgpr_1024 = COPY %4.sub0_sub1
; RA: %6.sub2:sgpr_1024 = COPY %6.sub0
; RA: %6.sub3:sgpr_1024 = COPY %6.sub1
; RA: %6.sub4:sgpr_1024 = COPY %6.sub0
; RA: %6.sub5:sgpr_1024 = COPY %6.sub1
; RA: %6.sub6:sgpr_1024 = COPY %6.sub0
; RA: %6.sub7:sgpr_1024 = COPY %6.sub1
; RA: %6.sub8:sgpr_1024 = COPY %6.sub0
; RA: %6.sub9:sgpr_1024 = COPY %6.sub1
; RA: %6.sub10:sgpr_1024 = COPY %6.sub0
; RA: %6.sub11:sgpr_1024 = COPY %6.sub1
; RA: %6.sub12:sgpr_1024 = COPY %6.sub0
; RA: %6.sub13:sgpr_1024 = COPY %6.sub1
; RA: %6.sub14:sgpr_1024 = COPY %6.sub0
; RA: %6.sub15:sgpr_1024 = COPY %6.sub1
; RA: %6.sub16:sgpr_1024 = COPY %6.sub0
; RA: %6.sub17:sgpr_1024 = COPY %6.sub1
; RA: %6.sub18:sgpr_1024 = COPY %6.sub0
; RA: %6.sub19:sgpr_1024 = COPY %6.sub1
; RA: %6.sub20:sgpr_1024 = COPY %6.sub0
; RA: %6.sub21:sgpr_1024 = COPY %6.sub1
; RA: %6.sub22:sgpr_1024 = COPY %6.sub0
; RA: %6.sub23:sgpr_1024 = COPY %6.sub1
; RA: %6.sub24:sgpr_1024 = COPY %6.sub0
; RA: %6.sub25:sgpr_1024 = COPY %6.sub1
; RA: %6.sub26:sgpr_1024 = COPY %6.sub0
; RA: %6.sub27:sgpr_1024 = COPY %6.sub1
; RA: %6.sub28:sgpr_1024 = COPY %6.sub0
; RA: %6.sub29:sgpr_1024 = COPY %6.sub1
; RA: undef %4.sub0_sub1:sgpr_1024 = COPY %6.sub0_sub1
; RA: %3.sub1:sgpr_1024 = COPY %3.sub0
; RA: %3.sub2:sgpr_1024 = COPY %3.sub0
; RA: %3.sub3:sgpr_1024 = COPY %3.sub0
; RA: %3.sub4:sgpr_1024 = COPY %3.sub0
; RA: %3.sub5:sgpr_1024 = COPY %3.sub0
; RA: %3.sub6:sgpr_1024 = COPY %3.sub0
; RA: %3.sub7:sgpr_1024 = COPY %3.sub0
; RA: %3.sub8:sgpr_1024 = COPY %3.sub0
; RA: %3.sub9:sgpr_1024 = COPY %3.sub0
; RA: %3.sub10:sgpr_1024 = COPY %3.sub0
; RA: %3.sub11:sgpr_1024 = COPY %3.sub0
; RA: %3.sub12:sgpr_1024 = COPY %3.sub0
; RA: %3.sub13:sgpr_1024 = COPY %3.sub0
; RA: %3.sub14:sgpr_1024 = COPY %3.sub0
; RA: %3.sub15:sgpr_1024 = COPY %3.sub0
; RA: %3.sub16:sgpr_1024 = COPY %3.sub0
; RA: %3.sub17:sgpr_1024 = COPY %3.sub0
; RA: %3.sub18:sgpr_1024 = COPY %3.sub0
; RA: %3.sub19:sgpr_1024 = COPY %3.sub0
; RA: %3.sub20:sgpr_1024 = COPY %3.sub0
; RA: %3.sub21:sgpr_1024 = COPY %3.sub0
; RA: %3.sub22:sgpr_1024 = COPY %3.sub0
; RA: %3.sub23:sgpr_1024 = COPY %3.sub0
; RA: %3.sub24:sgpr_1024 = COPY %3.sub0
; RA: %3.sub25:sgpr_1024 = COPY %3.sub0
; RA: %3.sub26:sgpr_1024 = COPY %3.sub0
; RA: %3.sub27:sgpr_1024 = COPY %3.sub0
; RA: %3.sub28:sgpr_1024 = COPY %3.sub0
; RA: %3.sub29:sgpr_1024 = COPY %3.sub0
; RA: %3.sub30:sgpr_1024 = COPY %3.sub0
; RA: %3.sub31:sgpr_1024 = COPY %3.sub0
; RA: bb.2:
; RA: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; RA: S_NOP 0, csr_amdgpu_highregs, implicit [[DEF]], implicit [[DEF1]]
; RA: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
; RA: S_BRANCH %bb.2
; VR-LABEL: name: splitkit_copy_bundle
; VR: bb.0:
; VR: successors: %bb.1(0x80000000)
; VR: renamable $sgpr69 = S_MOV_B32 -1
; VR: renamable $sgpr68 = S_MOV_B32 -1
; VR: renamable $sgpr36 = S_MOV_B32 0
; VR: renamable $sgpr34_sgpr35 = IMPLICIT_DEF
; VR: renamable $sgpr70_sgpr71 = IMPLICIT_DEF
; VR: bb.1:
; VR: successors: %bb.2(0x80000000)
; VR: liveins: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67:0x0000000000000003, $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99:0x000000000000000F, $sgpr34_sgpr35, $sgpr70_sgpr71
; VR: renamable $sgpr40_sgpr41 = COPY killed renamable $sgpr68_sgpr69
; VR: renamable $sgpr42 = COPY renamable $sgpr40
; VR: renamable $sgpr43 = COPY renamable $sgpr41
; VR: renamable $sgpr44 = COPY renamable $sgpr40
; VR: renamable $sgpr45 = COPY renamable $sgpr41
; VR: renamable $sgpr46 = COPY renamable $sgpr40
; VR: renamable $sgpr47 = COPY renamable $sgpr41
; VR: renamable $sgpr48 = COPY renamable $sgpr40
; VR: renamable $sgpr49 = COPY renamable $sgpr41
; VR: renamable $sgpr50 = COPY renamable $sgpr40
; VR: renamable $sgpr51 = COPY renamable $sgpr41
; VR: renamable $sgpr52 = COPY renamable $sgpr40
; VR: renamable $sgpr53 = COPY renamable $sgpr41
; VR: renamable $sgpr54 = COPY renamable $sgpr40
; VR: renamable $sgpr55 = COPY renamable $sgpr41
; VR: renamable $sgpr56 = COPY renamable $sgpr40
; VR: renamable $sgpr57 = COPY renamable $sgpr41
; VR: renamable $sgpr58 = COPY renamable $sgpr40
; VR: renamable $sgpr59 = COPY renamable $sgpr41
; VR: renamable $sgpr60 = COPY renamable $sgpr40
; VR: renamable $sgpr61 = COPY renamable $sgpr41
; VR: renamable $sgpr62 = COPY renamable $sgpr40
; VR: renamable $sgpr63 = COPY renamable $sgpr41
; VR: renamable $sgpr64 = COPY renamable $sgpr40
; VR: renamable $sgpr65 = COPY renamable $sgpr41
; VR: renamable $sgpr66 = COPY renamable $sgpr40
; VR: renamable $sgpr67 = COPY renamable $sgpr41
; VR: renamable $sgpr68 = COPY renamable $sgpr40
; VR: renamable $sgpr69 = COPY renamable $sgpr41
; VR: renamable $sgpr68_sgpr69 = COPY killed renamable $sgpr40_sgpr41
; VR: renamable $sgpr37 = COPY renamable $sgpr36
; VR: renamable $sgpr38 = COPY renamable $sgpr36
; VR: renamable $sgpr39 = COPY renamable $sgpr36
; VR: renamable $sgpr40 = COPY renamable $sgpr36
; VR: renamable $sgpr41 = COPY renamable $sgpr36
; VR: renamable $sgpr42 = COPY renamable $sgpr36
; VR: renamable $sgpr43 = COPY renamable $sgpr36
; VR: renamable $sgpr44 = COPY renamable $sgpr36
; VR: renamable $sgpr45 = COPY renamable $sgpr36
; VR: renamable $sgpr46 = COPY renamable $sgpr36
; VR: renamable $sgpr47 = COPY renamable $sgpr36
; VR: renamable $sgpr48 = COPY renamable $sgpr36
; VR: renamable $sgpr49 = COPY renamable $sgpr36
; VR: renamable $sgpr50 = COPY renamable $sgpr36
; VR: renamable $sgpr51 = COPY renamable $sgpr36
; VR: renamable $sgpr52 = COPY renamable $sgpr36
; VR: renamable $sgpr53 = COPY renamable $sgpr36
; VR: renamable $sgpr54 = COPY renamable $sgpr36
; VR: renamable $sgpr55 = COPY renamable $sgpr36
; VR: renamable $sgpr56 = COPY renamable $sgpr36
; VR: renamable $sgpr57 = COPY renamable $sgpr36
; VR: renamable $sgpr58 = COPY renamable $sgpr36
; VR: renamable $sgpr59 = COPY renamable $sgpr36
; VR: renamable $sgpr60 = COPY renamable $sgpr36
; VR: renamable $sgpr61 = COPY renamable $sgpr36
; VR: renamable $sgpr62 = COPY renamable $sgpr36
; VR: renamable $sgpr63 = COPY renamable $sgpr36
; VR: renamable $sgpr64 = COPY renamable $sgpr36
; VR: renamable $sgpr65 = COPY renamable $sgpr36
; VR: renamable $sgpr66 = COPY renamable $sgpr36
; VR: renamable $sgpr67 = COPY renamable $sgpr36
; VR: bb.2:
; VR: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; VR: liveins: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67:0x0000000000000003, $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99:0x000000000000000F, $sgpr34_sgpr35, $sgpr70_sgpr71
; VR: S_NOP 0, csr_amdgpu_highregs, implicit renamable $sgpr34_sgpr35, implicit renamable $sgpr70_sgpr71
; VR: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
; VR: S_BRANCH %bb.2
bb.0:
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = IMPLICIT_DEF
undef %2.sub1:sgpr_1024 = S_MOV_B32 -1
%2.sub0:sgpr_1024 = S_MOV_B32 -1
undef %3.sub0:sgpr_1024 = S_MOV_B32 0
bb.1:
%2.sub2:sgpr_1024 = COPY %2.sub0
%2.sub3:sgpr_1024 = COPY %2.sub1
%2.sub4:sgpr_1024 = COPY %2.sub0
%2.sub5:sgpr_1024 = COPY %2.sub1
%2.sub6:sgpr_1024 = COPY %2.sub0
%2.sub7:sgpr_1024 = COPY %2.sub1
%2.sub8:sgpr_1024 = COPY %2.sub0
%2.sub9:sgpr_1024 = COPY %2.sub1
%2.sub10:sgpr_1024 = COPY %2.sub0
%2.sub11:sgpr_1024 = COPY %2.sub1
%2.sub12:sgpr_1024 = COPY %2.sub0
%2.sub13:sgpr_1024 = COPY %2.sub1
%2.sub14:sgpr_1024 = COPY %2.sub0
%2.sub15:sgpr_1024 = COPY %2.sub1
%2.sub16:sgpr_1024 = COPY %2.sub0
%2.sub17:sgpr_1024 = COPY %2.sub1
%2.sub18:sgpr_1024 = COPY %2.sub0
%2.sub19:sgpr_1024 = COPY %2.sub1
%2.sub20:sgpr_1024 = COPY %2.sub0
%2.sub21:sgpr_1024 = COPY %2.sub1
%2.sub22:sgpr_1024 = COPY %2.sub0
%2.sub23:sgpr_1024 = COPY %2.sub1
%2.sub24:sgpr_1024 = COPY %2.sub0
%2.sub25:sgpr_1024 = COPY %2.sub1
%2.sub26:sgpr_1024 = COPY %2.sub0
%2.sub27:sgpr_1024 = COPY %2.sub1
%2.sub28:sgpr_1024 = COPY %2.sub0
%2.sub29:sgpr_1024 = COPY %2.sub1
%3.sub1:sgpr_1024 = COPY %3.sub0
%3.sub2:sgpr_1024 = COPY %3.sub0
%3.sub3:sgpr_1024 = COPY %3.sub0
%3.sub4:sgpr_1024 = COPY %3.sub0
%3.sub5:sgpr_1024 = COPY %3.sub0
%3.sub6:sgpr_1024 = COPY %3.sub0
%3.sub7:sgpr_1024 = COPY %3.sub0
%3.sub8:sgpr_1024 = COPY %3.sub0
%3.sub9:sgpr_1024 = COPY %3.sub0
%3.sub10:sgpr_1024 = COPY %3.sub0
%3.sub11:sgpr_1024 = COPY %3.sub0
%3.sub12:sgpr_1024 = COPY %3.sub0
%3.sub13:sgpr_1024 = COPY %3.sub0
%3.sub14:sgpr_1024 = COPY %3.sub0
%3.sub15:sgpr_1024 = COPY %3.sub0
%3.sub16:sgpr_1024 = COPY %3.sub0
%3.sub17:sgpr_1024 = COPY %3.sub0
%3.sub18:sgpr_1024 = COPY %3.sub0
%3.sub19:sgpr_1024 = COPY %3.sub0
%3.sub20:sgpr_1024 = COPY %3.sub0
%3.sub21:sgpr_1024 = COPY %3.sub0
%3.sub22:sgpr_1024 = COPY %3.sub0
%3.sub23:sgpr_1024 = COPY %3.sub0
%3.sub24:sgpr_1024 = COPY %3.sub0
%3.sub25:sgpr_1024 = COPY %3.sub0
%3.sub26:sgpr_1024 = COPY %3.sub0
%3.sub27:sgpr_1024 = COPY %3.sub0
%3.sub28:sgpr_1024 = COPY %3.sub0
%3.sub29:sgpr_1024 = COPY %3.sub0
%3.sub30:sgpr_1024 = COPY %3.sub0
%3.sub31:sgpr_1024 = COPY %3.sub0
bb.2:
S_NOP 0, implicit %0, implicit %1, csr_amdgpu_highregs
S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
S_BRANCH %bb.2
...
---
name: splitkit_copy_unbundle_reorder
tracksRegLiveness: true
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
; RA-LABEL: name: splitkit_copy_unbundle_reorder
; RA: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
; RA: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; RA: [[DEF2:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
; RA: [[DEF2]].sub4:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub5:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub10:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub11:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub7:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub8:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub13:sgpr_512 = S_MOV_B32 -1
; RA: [[DEF2]].sub14:sgpr_512 = S_MOV_B32 -1
; RA: undef %15.sub4_sub5:sgpr_512 = COPY [[DEF2]].sub4_sub5 {
; RA: internal %15.sub10_sub11:sgpr_512 = COPY [[DEF2]].sub10_sub11
; RA: internal %15.sub7:sgpr_512 = COPY [[DEF2]].sub7
; RA: internal %15.sub8:sgpr_512 = COPY [[DEF2]].sub8
; RA: internal %15.sub13:sgpr_512 = COPY [[DEF2]].sub13
; RA: internal %15.sub14:sgpr_512 = COPY [[DEF2]].sub14
; RA: }
; RA: SI_SPILL_S512_SAVE %15, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (store 64 into %stack.0, align 4, addrspace 5)
; RA: S_NOP 0, implicit-def $sgpr8, implicit-def $sgpr12, implicit-def $sgpr16, implicit-def $sgpr20, implicit-def $sgpr24, implicit-def $sgpr28, implicit-def $sgpr32, implicit-def $sgpr36, implicit-def $sgpr40, implicit-def $sgpr44, implicit-def $sgpr48, implicit-def $sgpr52, implicit-def $sgpr56, implicit-def $sgpr60, implicit-def $sgpr64, implicit-def $sgpr68, implicit-def $sgpr72, implicit-def $sgpr74, implicit-def $sgpr78, implicit-def $sgpr82, implicit-def $sgpr86, implicit-def $sgpr90, implicit-def $sgpr94, implicit-def $sgpr98
; RA: [[SI_SPILL_S512_RESTORE:%[0-9]+]]:sgpr_512 = SI_SPILL_S512_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (load 64 from %stack.0, align 4, addrspace 5)
; RA: undef %14.sub4_sub5:sgpr_512 = COPY [[SI_SPILL_S512_RESTORE]].sub4_sub5 {
; RA: internal %14.sub10_sub11:sgpr_512 = COPY [[SI_SPILL_S512_RESTORE]].sub10_sub11
; RA: internal %14.sub7:sgpr_512 = COPY [[SI_SPILL_S512_RESTORE]].sub7
; RA: internal %14.sub8:sgpr_512 = COPY [[SI_SPILL_S512_RESTORE]].sub8
; RA: internal %14.sub13:sgpr_512 = COPY [[SI_SPILL_S512_RESTORE]].sub13
; RA: internal %14.sub14:sgpr_512 = COPY [[SI_SPILL_S512_RESTORE]].sub14
; RA: }
; RA: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub4, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub5, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub10, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub11, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub7, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub8, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub13, 0, 0 :: (dereferenceable invariant load 4)
; RA: [[S_BUFFER_LOAD_DWORD_SGPR7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub14, 0, 0 :: (dereferenceable invariant load 4)
; RA: S_NOP 0, implicit [[DEF]], implicit [[DEF1]], implicit [[S_BUFFER_LOAD_DWORD_SGPR]], implicit [[S_BUFFER_LOAD_DWORD_SGPR1]], implicit [[S_BUFFER_LOAD_DWORD_SGPR2]], implicit [[S_BUFFER_LOAD_DWORD_SGPR3]], implicit [[S_BUFFER_LOAD_DWORD_SGPR4]], implicit [[S_BUFFER_LOAD_DWORD_SGPR5]], implicit [[S_BUFFER_LOAD_DWORD_SGPR6]], implicit [[S_BUFFER_LOAD_DWORD_SGPR7]]
; VR-LABEL: name: splitkit_copy_unbundle_reorder
; VR: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = IMPLICIT_DEF
; VR: renamable $sgpr16 = S_MOV_B32 -1
; VR: renamable $sgpr17 = S_MOV_B32 -1
; VR: renamable $sgpr22 = S_MOV_B32 -1
; VR: renamable $sgpr23 = S_MOV_B32 -1
; VR: renamable $sgpr19 = S_MOV_B32 -1
; VR: renamable $sgpr20 = S_MOV_B32 -1
; VR: renamable $sgpr25 = S_MOV_B32 -1
; VR: renamable $sgpr26 = S_MOV_B32 -1
; VR: SI_SPILL_S512_SAVE killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (store 64 into %stack.0, align 4, addrspace 5)
; VR: S_NOP 0, implicit-def $sgpr8, implicit-def $sgpr12, implicit-def $sgpr16, implicit-def $sgpr20, implicit-def $sgpr24, implicit-def $sgpr28, implicit-def $sgpr32, implicit-def $sgpr36, implicit-def $sgpr40, implicit-def $sgpr44, implicit-def $sgpr48, implicit-def $sgpr52, implicit-def $sgpr56, implicit-def $sgpr60, implicit-def $sgpr64, implicit-def $sgpr68, implicit-def $sgpr72, implicit-def $sgpr74, implicit-def $sgpr78, implicit-def $sgpr82, implicit-def $sgpr86, implicit-def $sgpr90, implicit-def $sgpr94, implicit-def $sgpr98
; VR: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = SI_SPILL_S512_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (load 64 from %stack.0, align 4, addrspace 5)
; VR: renamable $sgpr12_sgpr13 = COPY killed renamable $sgpr16_sgpr17
; VR: renamable $sgpr15 = COPY killed renamable $sgpr19
; VR: renamable $sgpr18_sgpr19 = COPY killed renamable $sgpr22_sgpr23
; VR: renamable $sgpr16 = COPY killed renamable $sgpr20
; VR: renamable $sgpr21 = COPY killed renamable $sgpr25
; VR: renamable $sgpr22 = COPY killed renamable $sgpr26
; VR: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = IMPLICIT_DEF
; VR: renamable $sgpr8 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr12, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr9 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr13, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr14 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr15, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr15 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr16, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr10_sgpr11 = IMPLICIT_DEF
; VR: renamable $sgpr12 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr18, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr13 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr19, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr16 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr21, 0, 0 :: (dereferenceable invariant load 4)
; VR: renamable $sgpr17 = S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr22, 0, 0 :: (dereferenceable invariant load 4)
; VR: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, implicit killed renamable $sgpr10_sgpr11, implicit killed renamable $sgpr8, implicit killed renamable $sgpr9, implicit killed renamable $sgpr12, implicit killed renamable $sgpr13, implicit killed renamable $sgpr14, implicit killed renamable $sgpr15, implicit killed renamable $sgpr16, implicit killed renamable $sgpr17
%0:sgpr_128 = IMPLICIT_DEF
%1:sreg_64 = IMPLICIT_DEF
%2:sgpr_512 = IMPLICIT_DEF
%2.sub4:sgpr_512 = S_MOV_B32 -1
%2.sub5:sgpr_512 = S_MOV_B32 -1
%2.sub10:sgpr_512 = S_MOV_B32 -1
%2.sub11:sgpr_512 = S_MOV_B32 -1
%2.sub7:sgpr_512 = S_MOV_B32 -1
%2.sub8:sgpr_512 = S_MOV_B32 -1
%2.sub13:sgpr_512 = S_MOV_B32 -1
%2.sub14:sgpr_512 = S_MOV_B32 -1
; Clobber registers
S_NOP 0, implicit-def $sgpr8, implicit-def $sgpr12, implicit-def $sgpr16, implicit-def $sgpr20, implicit-def $sgpr24, implicit-def $sgpr28, implicit-def $sgpr32, implicit-def $sgpr36, implicit-def $sgpr40, implicit-def $sgpr44, implicit-def $sgpr48, implicit-def $sgpr52, implicit-def $sgpr56, implicit-def $sgpr60, implicit-def $sgpr64, implicit-def $sgpr68, implicit-def $sgpr72, implicit-def $sgpr74, implicit-def $sgpr78, implicit-def $sgpr82, implicit-def $sgpr86, implicit-def $sgpr90, implicit-def $sgpr94, implicit-def $sgpr98
%5:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub4:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%6:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub5:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%7:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub10:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%8:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub11:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub7:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%10:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub8:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%11:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub13:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
%12:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub14:sgpr_512, 0, 0 :: (dereferenceable invariant load 4)
S_NOP 0, implicit %0, implicit %1, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12
...
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