Matt Arsenault c765240060
AMDGPU/GlobalISel: Introduce vcc reg bank ...
I'm not entirely sure this is the correct thing
to do with the global isel philosophy, but I think
this is necessary to handle how differently SGPRs
are used normally vs. from a condition.
For example, it makes sense to allow a copy
from a VGPR to an SGPR, but it makes no sense
to allow a copy from VGPRs to SGPRs used as
select mask.
This avoids regbankselecting strange code with
a truncate feeding directly into a condition field.
Now a copy is forced from sgpr(s1) to vcc, which is
more sensible to handle.
Some of these issues could probably avoided with making enough
operations resulting in i1 illegal. I think we can't avoid
this register bank for legality.
For example, an i1 and where one source is from a truncate, and
one source is a compare needs some kind of copy inserted to
make sure both are in condition registers.
llvm-svn: 350611
2019-01-08 06:30:53 +00:00
2018-10-08 17:49:29 +00:00
2018-10-05 04:34:09 +00:00
2018-12-13 08:11:45 +00:00
2018-12-20 01:35:49 +00:00
2018-12-13 08:11:45 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-13 08:11:45 +00:00
2018-12-13 20:34:15 +00:00
2019-01-08 01:22:47 +00:00
2018-12-21 03:03:11 +00:00
2019-01-08 01:30:02 +00:00
2018-12-10 18:44:58 +00:00
2018-12-18 09:19:03 +00:00
2018-12-13 08:27:48 +00:00
2018-12-13 08:11:45 +00:00
2018-12-18 09:39:56 +00:00
2018-12-13 08:27:48 +00:00
2018-12-18 09:19:03 +00:00
2018-12-13 08:11:45 +00:00
2018-12-20 00:37:02 +00:00
2018-12-18 09:19:03 +00:00
2018-12-13 08:11:45 +00:00
2018-12-21 03:14:45 +00:00
2018-12-21 03:14:45 +00:00
2018-10-05 04:34:09 +00:00
2018-12-10 18:44:58 +00:00
2018-12-20 01:35:49 +00:00
2018-12-13 08:11:45 +00:00
2018-12-13 08:11:45 +00:00
2018-12-10 18:44:58 +00:00
2018-12-20 01:35:49 +00:00
2019-01-08 06:30:53 +00:00
2019-01-08 06:30:53 +00:00
2018-12-13 08:23:51 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-20 00:33:49 +00:00
2018-12-13 20:34:15 +00:00
2019-01-08 06:30:53 +00:00
2018-12-13 08:23:51 +00:00
2018-12-13 08:23:51 +00:00
2018-12-13 08:23:51 +00:00
2018-12-13 08:23:51 +00:00
2018-12-13 08:23:51 +00:00
2018-12-13 08:23:51 +00:00
2018-12-18 09:19:03 +00:00
2019-01-08 06:30:53 +00:00
2018-12-21 03:14:45 +00:00
2018-12-21 03:14:45 +00:00
2018-12-18 09:39:56 +00:00
2018-12-18 09:19:03 +00:00
2018-12-20 00:37:02 +00:00
2018-12-18 09:46:13 +00:00
2018-12-19 09:07:58 +00:00
2019-01-08 06:30:53 +00:00
2018-08-11 00:51:54 +00:00
2018-12-21 03:14:45 +00:00
2018-12-21 03:14:45 +00:00
2018-10-05 04:34:09 +00:00
2018-12-20 01:35:49 +00:00
2018-12-13 08:23:51 +00:00
2019-01-08 06:30:53 +00:00
2019-01-08 06:30:53 +00:00
2019-01-08 06:30:53 +00:00
2018-12-13 08:23:51 +00:00
2018-12-20 00:37:02 +00:00
2019-01-08 06:30:53 +00:00
2019-01-08 06:30:53 +00:00
2018-12-20 01:33:43 +00:00
2019-01-08 06:30:53 +00:00
2019-01-08 06:30:53 +00:00
2018-12-20 00:37:02 +00:00
2019-01-08 00:46:19 +00:00
2019-01-08 06:30:53 +00:00
2019-01-08 06:30:53 +00:00
2018-12-20 01:35:49 +00:00
c765240060