Wouter van Oortmerssen 820c6263d9 [WebAssembly] Fixed disassembler not knowing about new brlist operand ...

Summary:
The previously introduced new operand type for br_table didn't have
a disassembler implementation, causing an assert.

Reviewers: dschuff, aheejin

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56227

llvm-svn: 350366

2019-01-03 23:01:30 +00:00

..

AsmMatcherEmitter.cpp

Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC

2018-10-19 06:12:02 +00:00

AsmWriterEmitter.cpp

[TableGen:AsmWriter] Cope with consecutive tied operands.

2018-12-14 11:39:55 +00:00

AsmWriterInst.cpp

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AsmWriterInst.h

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Attributes.cpp

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CallingConvEmitter.cpp

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CMakeLists.txt

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

CodeEmitterGen.cpp

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CodeGenDAGPatterns.cpp

[TableGen] Preserve order of output operands in DAGISelMatcherGen

2018-12-05 00:47:59 +00:00

CodeGenDAGPatterns.h

[TableGen] Preserve order of output operands in DAGISelMatcherGen

2018-12-05 00:47:59 +00:00

CodeGenHwModes.cpp

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CodeGenHwModes.h

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CodeGenInstruction.cpp

[ARM][MC] Move information about variadic register defs into tablegen

2018-12-03 10:32:42 +00:00

CodeGenInstruction.h

[ARM][MC] Move information about variadic register defs into tablegen

2018-12-03 10:32:42 +00:00

CodeGenIntrinsics.h

Mark @llvm.trap cold

2018-11-14 19:53:41 +00:00

CodeGenMapTable.cpp

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CodeGenRegisters.cpp

[TableGen] Examine entire subreg compositions to detect ambiguity

2018-11-29 18:20:08 +00:00

CodeGenRegisters.h

[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum

2018-08-16 15:29:24 +00:00

CodeGenSchedule.cpp

[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).

2018-11-29 12:15:56 +00:00

CodeGenSchedule.h

[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).

2018-11-29 12:15:56 +00:00

CodeGenTarget.cpp

Mark @llvm.trap cold

2018-11-14 19:53:41 +00:00

CodeGenTarget.h

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CTagsEmitter.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

DAGISelEmitter.cpp

[TableGen] Support multi-alternative pattern fragments

2018-07-13 13:18:00 +00:00

DAGISelMatcher.cpp

TableGen/ISel: Allow PatFrag predicate code to access captured operands

2018-11-30 14:15:13 +00:00

DAGISelMatcher.h

TableGen/ISel: Allow PatFrag predicate code to access captured operands

2018-11-30 14:15:13 +00:00

DAGISelMatcherEmitter.cpp

TableGen/ISel: Allow PatFrag predicate code to access captured operands

2018-11-30 14:15:13 +00:00

DAGISelMatcherGen.cpp

[TableGen] Preserve order of output operands in DAGISelMatcherGen

2018-12-05 00:47:59 +00:00

DAGISelMatcherOpt.cpp

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DFAPacketizerEmitter.cpp

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DisassemblerEmitter.cpp

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ExegesisEmitter.cpp

[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.

2018-11-09 13:15:32 +00:00

FastISelEmitter.cpp

TableGen/ISel: Allow PatFrag predicate code to access captured operands

2018-11-30 14:15:13 +00:00

FixedLenDecoderEmitter.cpp

[tblgen][disasm] Emit record names again when decoder conflicts occur.

2019-01-03 00:14:33 +00:00

GlobalISelEmitter.cpp

TableGen/ISel: Allow PatFrag predicate code to access captured operands

2018-11-30 14:15:13 +00:00

InfoByHwMode.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

InfoByHwMode.h

[TableGen] Don't separately search for DefaultMode when we're going to iterate the set anyway. NFCI.

2018-08-17 17:45:15 +00:00

InstrDocsEmitter.cpp

[ARM][MC] Move information about variadic register defs into tablegen

2018-12-03 10:32:42 +00:00

InstrInfoEmitter.cpp

[TableGen] Improve the formatting of the emitted predicates (NFC)

2018-12-04 01:43:22 +00:00

IntrinsicEmitter.cpp

Mark @llvm.trap cold

2018-11-14 19:53:41 +00:00

LLVMBuild.txt

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OptParserEmitter.cpp

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PredicateExpander.cpp

[TableGen] Fix negation of simple predicates

2018-11-30 21:03:24 +00:00

PredicateExpander.h

[tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands.

2018-10-31 12:28:05 +00:00

PseudoLoweringEmitter.cpp

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RegisterBankEmitter.cpp

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RegisterInfoEmitter.cpp

Use the container form llvm::sort(C)

2018-10-31 00:31:06 +00:00

RISCVCompressInstEmitter.cpp

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SDNodeProperties.cpp

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SDNodeProperties.h

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SearchableTableEmitter.cpp

TableGen: Fix ASAN error

2018-10-31 17:46:21 +00:00

SequenceToOffsetTable.h

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SubtargetEmitter.cpp

[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).

2018-11-29 12:15:56 +00:00

SubtargetFeatureInfo.cpp

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SubtargetFeatureInfo.h

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TableGen.cpp

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

TableGenBackends.h

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

tdtags

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Types.cpp

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Types.h

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WebAssemblyDisassemblerEmitter.cpp

[WebAssembly] Fixed disassembler not knowing about new brlist operand

2019-01-03 23:01:30 +00:00

WebAssemblyDisassemblerEmitter.h

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X86DisassemblerShared.h

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X86DisassemblerTables.cpp

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X86DisassemblerTables.h

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X86EVEX2VEXTablesEmitter.cpp

[X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter.

2018-06-19 04:24:44 +00:00

X86FoldTablesEmitter.cpp

[X86] More additions to the load folding tables based on the autogenerated tables.

2018-06-16 23:25:50 +00:00

X86ModRMFilters.cpp

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X86ModRMFilters.h

Test commit: remove trailing whitespace

2018-09-11 17:28:43 +00:00

X86RecognizableInstr.cpp

[X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.

2018-08-13 22:06:28 +00:00

X86RecognizableInstr.h

[X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0.

2018-06-19 04:24:42 +00:00