Simon Pilgrim 3fc09f7be6 [CostModel][X86][SSE] Updated costs for vector BITREVERSE ops on SSSE3+ targets ...

To account for the fast PSHUFB implementation now available

llvm-svn: 272484

2016-06-11 19:23:02 +00:00

..

AArch64

[TTI] Add hook for vector extract with extension

2016-04-27 15:20:21 +00:00

AMDGPU

[SLPVectorizer] Try different vectorization factors for store chains

2015-07-08 23:40:55 +00:00

ARM

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00

PowerPC

[SLP] Pass in correct alignment when query memory access cost

2016-05-31 20:41:19 +00:00

X86

[CostModel][X86][SSE] Updated costs for vector BITREVERSE ops on SSSE3+ targets

2016-06-11 19:23:02 +00:00

XCore

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00