521ebc1681
This matches the DAG behavior where this is called after the loop checking for calls. The AMDGPU implementation depends on knowing if there are calls in the function or not, so move this later. Another problem is finalizeLowering is actually called twice; I was seeing weird inconsistencies since the first call would produce unexpected results and the second run would correct them in some contexts. Since this requires disabling the verifier, and it's useful to serialize the MIR immediately after selection, FinalizeISel should probably not be a real pass.
262 lines
9.3 KiB
C++
262 lines
9.3 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InstructionSelect class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Config/config.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "instruction-select"
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using namespace llvm;
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#ifdef LLVM_GISEL_COV_PREFIX
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static cl::opt<std::string>
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CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
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cl::desc("Record GlobalISel rule coverage files of this "
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"prefix if instrumentation was generated"));
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#else
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static const std::string CoveragePrefix = "";
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#endif
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char InstructionSelect::ID = 0;
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INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
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"Select target instructions out of generic instructions",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
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"Select target instructions out of generic instructions",
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false, false)
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InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { }
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void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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getSelectionDAGFallbackAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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// If the ISel pipeline failed, do not bother running that pass.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
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GISelKnownBits &KB = getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
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InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
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CodeGenCoverage CoverageInfo;
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assert(ISel && "Cannot work without InstructionSelector");
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ISel->setupMF(MF, KB, CoverageInfo);
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// An optimization remark emitter. Used to report failures.
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MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
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// FIXME: There are many other MF/MFI fields we need to initialize.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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#ifndef NDEBUG
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// Check that our input is fully legal: we require the function to have the
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// Legalized property, so it should be.
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// FIXME: This should be in the MachineVerifier, as the RegBankSelected
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// property check already is.
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if (!DisableGISelLegalityCheck)
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if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
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reportGISelFailure(MF, TPC, MORE, "gisel-select",
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"instruction is not legal", *MI);
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return false;
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}
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// FIXME: We could introduce new blocks and will need to fix the outer loop.
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// Until then, keep track of the number of blocks to assert that we don't.
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const size_t NumBlocks = MF.size();
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#endif
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for (MachineBasicBlock *MBB : post_order(&MF)) {
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if (MBB->empty())
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continue;
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// Select instructions in reverse block order. We permit erasing so have
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// to resort to manually iterating and recognizing the begin (rend) case.
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bool ReachedBegin = false;
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for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
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!ReachedBegin;) {
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#ifndef NDEBUG
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// Keep track of the insertion range for debug printing.
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const auto AfterIt = std::next(MII);
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#endif
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// Select this instruction.
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MachineInstr &MI = *MII;
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// And have our iterator point to the next instruction, if there is one.
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if (MII == Begin)
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ReachedBegin = true;
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else
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--MII;
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LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
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// We could have folded this instruction away already, making it dead.
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// If so, erase it.
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if (isTriviallyDead(MI, MRI)) {
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LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
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MI.eraseFromParentAndMarkDBGValuesForRemoval();
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continue;
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}
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if (!ISel->select(MI)) {
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// FIXME: It would be nice to dump all inserted instructions. It's
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// not obvious how, esp. considering select() can insert after MI.
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reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
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return false;
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}
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// Dump the range of instructions that MI expanded into.
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LLVM_DEBUG({
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auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
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dbgs() << "Into:\n";
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for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
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dbgs() << " " << InsertedMI;
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dbgs() << '\n';
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});
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}
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}
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for (MachineBasicBlock &MBB : MF) {
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if (MBB.empty())
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continue;
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// Try to find redundant copies b/w vregs of the same register class.
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bool ReachedBegin = false;
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for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
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// Select this instruction.
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MachineInstr &MI = *MII;
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// And have our iterator point to the next instruction, if there is one.
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if (MII == Begin)
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ReachedBegin = true;
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else
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--MII;
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if (MI.getOpcode() != TargetOpcode::COPY)
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continue;
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Register SrcReg = MI.getOperand(1).getReg();
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Register DstReg = MI.getOperand(0).getReg();
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if (Register::isVirtualRegister(SrcReg) &&
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Register::isVirtualRegister(DstReg)) {
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auto SrcRC = MRI.getRegClass(SrcReg);
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auto DstRC = MRI.getRegClass(DstReg);
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if (SrcRC == DstRC) {
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MRI.replaceRegWith(DstReg, SrcReg);
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MI.eraseFromParent();
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}
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}
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}
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}
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#ifndef NDEBUG
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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// Now that selection is complete, there are no more generic vregs. Verify
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// that the size of the now-constrained vreg is unchanged and that it has a
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// register class.
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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unsigned VReg = Register::index2VirtReg(I);
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MachineInstr *MI = nullptr;
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if (!MRI.def_empty(VReg))
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MI = &*MRI.def_instr_begin(VReg);
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else if (!MRI.use_empty(VReg))
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MI = &*MRI.use_instr_begin(VReg);
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if (!MI)
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continue;
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const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
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if (!RC) {
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reportGISelFailure(MF, TPC, MORE, "gisel-select",
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"VReg has no regclass after selection", *MI);
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return false;
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}
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const LLT Ty = MRI.getType(VReg);
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if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
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reportGISelFailure(
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MF, TPC, MORE, "gisel-select",
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"VReg's low-level type and register class have different sizes", *MI);
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return false;
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}
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}
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if (MF.size() != NumBlocks) {
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MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
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MF.getFunction().getSubprogram(),
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/*MBB=*/nullptr);
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R << "inserting blocks is not supported yet";
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reportGISelFailure(MF, TPC, MORE, R);
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return false;
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}
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#endif
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// Determine if there are any calls in this machine function. Ported from
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// SelectionDAG.
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MachineFrameInfo &MFI = MF.getFrameInfo();
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for (const auto &MBB : MF) {
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if (MFI.hasCalls() && MF.hasInlineAsm())
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break;
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for (const auto &MI : MBB) {
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if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
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MFI.setHasCalls(true);
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if (MI.isInlineAsm())
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MF.setHasInlineAsm(true);
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}
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}
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// FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
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auto &TLI = *MF.getSubtarget().getTargetLowering();
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TLI.finalizeLowering(MF);
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LLVM_DEBUG({
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dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
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for (auto RuleID : CoverageInfo.covered())
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dbgs() << " id" << RuleID;
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dbgs() << "\n\n";
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});
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CoverageInfo.emit(CoveragePrefix,
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TLI.getTargetMachine().getTarget().getBackendName());
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// If we successfully selected the function nothing is going to use the vreg
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// types after us (otherwise MIRPrinter would need them). Make sure the types
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// disappear.
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MRI.clearVirtRegTypes();
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// FIXME: Should we accurately track changes?
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return true;
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}
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