6a089ce0e4
Use tablegen generic tables to get the index of image intrinsic arguments. Before, the computation of which image intrinsic argument is at which index was scattered in a few places, tablegen, the SDag instruction selection and GlobalISel. This patch changes that, so only tablegen contains code to compute indices and the ImageDimIntrinsicInfo table provides these information. Differential Revision: https://reviews.llvm.org/D86270
87 lines
2.1 KiB
C++
87 lines
2.1 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#include "AMDGPU.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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namespace llvm {
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class GCNSubtarget;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class AMDGPUInstrInfo {
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public:
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explicit AMDGPUInstrInfo(const GCNSubtarget &st);
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static bool isUniformMMO(const MachineMemOperand *MMO);
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};
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namespace AMDGPU {
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struct RsrcIntrinsic {
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unsigned Intr;
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uint8_t RsrcArg;
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bool IsImage;
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};
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const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
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struct D16ImageDimIntrinsic {
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unsigned Intr;
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unsigned D16HelperIntr;
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};
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const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
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struct ImageDimIntrinsicInfo {
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unsigned Intr;
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unsigned BaseOpcode;
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MIMGDim Dim;
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uint8_t NumGradients;
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uint8_t NumDmask;
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uint8_t NumData;
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uint8_t NumVAddrs;
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uint8_t NumArgs;
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uint8_t DMaskIndex;
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uint8_t VAddrStart;
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uint8_t GradientStart;
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uint8_t CoordStart;
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uint8_t LodIndex;
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uint8_t MipIndex;
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uint8_t VAddrEnd;
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uint8_t RsrcIndex;
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uint8_t SampIndex;
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uint8_t UnormIndex;
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uint8_t TexFailCtrlIndex;
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uint8_t CachePolicyIndex;
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uint8_t GradientTyArg;
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uint8_t CoordTyArg;
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};
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const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
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const ImageDimIntrinsicInfo *getImageDimInstrinsicByBaseOpcode(unsigned BaseOpcode,
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unsigned Dim);
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} // end AMDGPU namespace
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} // End llvm namespace
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#endif
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