b955c7e630
VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE vector instructions and the initial SDNodes. We introduce 'vvp_add' with isel and tests as the first of these VVP nodes. VVP nodes have a mask and explicit vector length operand, which we will make proper use of later. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91802
45 lines
1.7 KiB
TableGen
45 lines
1.7 KiB
TableGen
//===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the VEC_* prefixed intermediate SDNodes and their
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// isel patterns.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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multiclass vbrd_elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp, SDNodeXForm ImmCast, int SubRegIdx> {
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// VBRDil
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def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
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(VBRDil (ImmCast $sy), i32:$vl)>;
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// VBRDrl
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def : Pat<(v32 (vec_broadcast s32:$sy, i32:$vl)),
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(VBRDrl
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, SubRegIdx),
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i32:$vl)>;
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}
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defm : vbrd_elem32<v256f32, f32, simm7fp, LO7FP, sub_f32>;
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defm : vbrd_elem32<v256i32, i32, simm7, LO7, sub_i32>;
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multiclass vbrd_elem64<ValueType v64, ValueType s64, SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
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// VBRDil
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def : Pat<(v64 (vec_broadcast (s64 ImmOp:$sy), i32:$vl)),
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(VBRDil (ImmCast $sy), i32:$vl)>;
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// VBRDrl
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def : Pat<(v64 (vec_broadcast s64:$sy, i32:$vl)),
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(VBRDrl s64:$sy, i32:$vl)>;
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}
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defm : vbrd_elem64<v256f64, f64, simm7fp, LO7FP>;
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defm : vbrd_elem64<v256i64, i64, simm7, LO7>;
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