60b1967c39
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
132 lines
5.6 KiB
LLVM
132 lines
5.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s
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; FIXME: Vectorization can increase required SGPR count beyond limit.
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; ALL-LABEL: {{^}}max_10_sgprs:
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; ALL: SGPRBlocks: 1
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; ALL: NumSGPRsForWavesPerEU: 10
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define amdgpu_kernel void @max_10_sgprs() #0 {
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%one = load volatile i32, i32 addrspace(4)* undef
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%two = load volatile i32, i32 addrspace(4)* undef
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%three = load volatile i32, i32 addrspace(4)* undef
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%four = load volatile i32, i32 addrspace(4)* undef
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%five = load volatile i32, i32 addrspace(4)* undef
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%six = load volatile i32, i32 addrspace(4)* undef
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%seven = load volatile i32, i32 addrspace(4)* undef
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%eight = load volatile i32, i32 addrspace(4)* undef
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%nine = load volatile i32, i32 addrspace(4)* undef
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%ten = load volatile i32, i32 addrspace(4)* undef
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%eleven = load volatile i32, i32 addrspace(4)* undef
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call void asm sideeffect "", "s,s,s,s,s,s,s,s,s,s"(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, i32 %nine, i32 %ten)
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store volatile i32 %one, i32 addrspace(1)* undef
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store volatile i32 %two, i32 addrspace(1)* undef
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store volatile i32 %three, i32 addrspace(1)* undef
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store volatile i32 %four, i32 addrspace(1)* undef
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store volatile i32 %five, i32 addrspace(1)* undef
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store volatile i32 %six, i32 addrspace(1)* undef
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store volatile i32 %seven, i32 addrspace(1)* undef
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store volatile i32 %eight, i32 addrspace(1)* undef
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store volatile i32 %nine, i32 addrspace(1)* undef
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store volatile i32 %ten, i32 addrspace(1)* undef
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store volatile i32 %eleven, i32 addrspace(1)* undef
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ret void
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}
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; private resource: 4
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; scratch wave offset: 1
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; workgroup ids: 3
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; dispatch id: 2
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; queue ptr: 2
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; flat scratch init: 2
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; ---------------------
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; total: 14
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; + reserved vcc = 16
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; Because we can't handle re-using the last few input registers as the
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; special vcc etc. registers (as well as decide to not use the unused
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; features when the number of registers is frozen), this ends up using
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; more than expected.
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; XALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:
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; XTOSGPR: SGPRBlocks: 1
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; XTOSGPR: NumSGPRsForWavesPerEU: 16
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; This test case is disabled: When calculating the spillslot addresses AMDGPU
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; creates an extra vreg to save/restore m0 which in a point of maximum register
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; pressure would trigger an endless loop; the compiler aborts earlier with
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; "Incomplete scavenging after 2nd pass" in practice.
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;define amdgpu_kernel void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,
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; i32 addrspace(1)* %out2,
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; i32 addrspace(1)* %out3,
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; i32 addrspace(1)* %out4,
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; i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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; %x.3 = call i64 @llvm.amdgcn.dispatch.id()
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; %x.4 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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; %x.5 = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
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; store volatile i32 0, i32* undef
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; br label %stores
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;
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;stores:
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; store volatile i64 %x.3, i64 addrspace(1)* undef
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; store volatile i8 addrspace(4)* %x.4, i8 addrspace(4)* addrspace(1)* undef
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; store volatile i8 addrspace(4)* %x.5, i8 addrspace(4)* addrspace(1)* undef
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;
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; store i32 %one, i32 addrspace(1)* %out1
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; store i32 %two, i32 addrspace(1)* %out2
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; store i32 %three, i32 addrspace(1)* %out3
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; store i32 %four, i32 addrspace(1)* %out4
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; ret void
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;}
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; The following test is commented out for now; http://llvm.org/PR31230
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; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}
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; ; Make sure copies for input buffer are not clobbered. This requires
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; ; swapping the order the registers are copied from what normally
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; ; happens.
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; XALL: SGPRBlocks: 2
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; XALL: NumSGPRsForWavesPerEU: 18
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;define amdgpu_kernel void @max_12_sgprs_12_input_sgprs(i32 addrspace(1)* %out1,
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; i32 addrspace(1)* %out2,
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; i32 addrspace(1)* %out3,
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; i32 addrspace(1)* %out4,
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; i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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; store volatile i32 0, i32* undef
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; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.3 = call i64 @llvm.amdgcn.dispatch.id()
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; store volatile i64 %x.3, i64 addrspace(1)* undef
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; %x.4 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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; store volatile i8 addrspace(4)* %x.4, i8 addrspace(4)* addrspace(1)* undef
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;
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; store i32 %one, i32 addrspace(1)* %out1
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; store i32 %two, i32 addrspace(1)* %out2
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; store i32 %three, i32 addrspace(1)* %out3
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; store i32 %four, i32 addrspace(1)* %out4
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; ret void
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;}
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declare i32 @llvm.amdgcn.workgroup.id.x() #1
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declare i32 @llvm.amdgcn.workgroup.id.y() #1
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declare i32 @llvm.amdgcn.workgroup.id.z() #1
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declare i64 @llvm.amdgcn.dispatch.id() #1
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declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #1
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declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #1
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attributes #0 = { nounwind "amdgpu-num-sgpr"="14" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "amdgpu-num-sgpr"="12" }
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attributes #3 = { nounwind "amdgpu-num-sgpr"="11" }
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