d2e52eec51
Use the 64-bit SGPR base with a 0 offset, since it's 1 fewer instruction to materialize the 0 vs. the 64-bit copy.
153 lines
5.5 KiB
LLVM
153 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; Load argument depends on waitcnt which should be skipped.
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define amdgpu_kernel void @call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0 {
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; GCN-LABEL: call_memory_arg_load:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: ds_read_b32 v0, v0
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func@rel32@hi+12
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: s_endpgm
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%vgpr = load volatile i32, i32 addrspace(3)* %ptr
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call void @func(i32 %vgpr)
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ret void
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}
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; Memory waitcnt with no register dependence on the call
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define amdgpu_kernel void @call_memory_no_dep(i32 addrspace(1)* %ptr, i32) #0 {
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; GCN-LABEL: call_memory_no_dep:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_store_dword v0, v0, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6, s6, func@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s7, s7, func@rel32@hi+12
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GCN-NEXT: s_endpgm
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store i32 0, i32 addrspace(1)* %ptr
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call void @func(i32 0)
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ret void
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}
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; Should not wait after the call before memory
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define amdgpu_kernel void @call_no_wait_after_call(i32 addrspace(1)* %ptr, i32) #0 {
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; GCN-LABEL: call_no_wait_after_call:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x0
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func@rel32@hi+12
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: v_mov_b32_e32 v40, 0
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: global_store_dword v40, v40, s[34:35]
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; GCN-NEXT: s_endpgm
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call void @func(i32 0)
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store i32 0, i32 addrspace(1)* %ptr
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ret void
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}
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define amdgpu_kernel void @call_no_wait_after_call_return_val(i32 addrspace(1)* %ptr, i32) #0 {
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; GCN-LABEL: call_no_wait_after_call_return_val:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x0
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func.return@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func.return@rel32@hi+12
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: v_mov_b32_e32 v40, 0
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: global_store_dword v40, v0, s[34:35]
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; GCN-NEXT: s_endpgm
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%rv = call i32 @func.return(i32 0)
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store i32 %rv, i32 addrspace(1)* %ptr
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ret void
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}
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; Need to wait for the address dependency
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define amdgpu_kernel void @call_got_load(i32 addrspace(1)* %ptr, i32) #0 {
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; GCN-LABEL: call_got_load:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, got.func@gotpcrel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, got.func@gotpcrel32@hi+12
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: s_endpgm
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call void @got.func(i32 0)
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ret void
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}
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; Need to wait for the address dependency
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define void @tailcall_got_load(i32 addrspace(1)* %ptr, i32) #0 {
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; GCN-LABEL: tailcall_got_load:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, got.func@gotpcrel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, got.func@gotpcrel32@hi+12
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[4:5]
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tail call void @got.func(i32 0)
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ret void
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}
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; No need to wait for the load.
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define void @tail_call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0 {
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; GCN-LABEL: tail_call_memory_arg_load:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: ds_read_b32 v0, v0
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func@rel32@hi+12
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; GCN-NEXT: s_setpc_b64 s[4:5]
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%vgpr = load volatile i32, i32 addrspace(3)* %ptr
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tail call void @func(i32 %vgpr)
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ret void
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}
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declare hidden void @func(i32) #0
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declare hidden i32 @func.return(i32) #0
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declare void @got.func(i32) #0
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attributes #0 = { nounwind }
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