79298a5067
This was only used for matching the saddr addressing mode of global instructions, but this was not implemented correctly. The instruction definitions aren't even correct, and are defined as using a 64-bit VGPR component. Eliminate this pass to enable correcting the instruction definitions. A new matching implementation can work in GlobalISel or relying on DAG divergence information for the base address.
66 lines
3.5 KiB
LLVM
66 lines
3.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause
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; GCN: BUNDLE
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; GCN-NEXT: LOAD_DWORDX2
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; GCN-NEXT: LOAD_DWORDX2
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; GCN-NEXT: {{^ *[}]}}
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define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
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%tmp10 = add nuw nsw i64 %tmp2, 2
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%tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
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%tmp14 = add nuw nsw i64 %tmp2, 3
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%tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
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%tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
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%tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
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store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
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store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
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ret void
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}
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; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause
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; GCN-NOT: BUNDLE
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define amdgpu_kernel void @no_vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
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%tmp10 = add nuw nsw i64 %tmp2, 2
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%tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
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%tmp14 = add nuw nsw i64 %tmp2, 3
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%tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
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%tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
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%tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
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store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
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store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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attributes #0 = { "amdgpu-max-memory-clause"="1" }
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