4b4496312e
This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
33 lines
1.1 KiB
YAML
33 lines
1.1 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck -check-prefix=GFX90 %s
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# This tests that a KILL isn't considered as a valid instruction for a hazard
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# slot (e.g. m0 def followed by V_INTERP for gfx9)
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# The hazard recognizer should mov another instruction into that slot (in this case the S_MOV_B32
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--- |
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define amdgpu_ps void @_amdgpu_ps_main() #0 { ret void }
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...
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---
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# CHECK-LABEL: name: _amdgpu_ps_main
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# CHECK-LABEL: bb.0:
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# GFX90: $m0 = S_MOV_B32 killed renamable $sgpr4
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# GFX90-NEXT: KILL undef renamable $sgpr2
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# GFX90-NEXT: S_MOV_B32 0
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# GFX90-NEXT: V_INTERP_MOV_F32
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name: _amdgpu_ps_main
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr2, $sgpr3, $sgpr4
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$sgpr6 = S_MOV_B32 killed $sgpr3
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renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0, 0
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$m0 = S_MOV_B32 killed renamable $sgpr4
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dead renamable $sgpr0 = KILL undef renamable $sgpr2
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renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $mode, implicit $m0, implicit $exec
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renamable $sgpr0 = S_MOV_B32 0
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S_ENDPGM 0
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...
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