615f63e149
This reverts commitcf1c774d6a. This change caused several regressions in the gdb test suite - at least a sample of which was due to line zero instructions making breakpoints un-lined. I think they're worth investigating/understanding more (& possibly addressing) before moving forward with this change. Revert "[FastISel] NFC: Clean up unnecessary bookkeeping" This reverts commit3fd39d3694. Revert "[FastISel] NFC: Remove obsolete -fast-isel-sink-local-values option" This reverts commita474657e30. Revert "Remove static function unused after cf1c774." This reverts commitdc35368ccf. Revert "[lldb] Fix TestThreadStepOut.py after "Flush local value map on every instruction"" This reverts commit53a14a47ee.
46 lines
1.6 KiB
LLVM
46 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O0 < %s \
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; RUN: | FileCheck -check-prefix=NOOPT %s
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; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck -check-prefix=STATIC %s
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck -check-prefix=PIC %s
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; Test correct code generation for static and pic for loading and storing a common symbol
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@comm_glob = common global i32 0, align 4
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define signext i32 @test_comm() nounwind {
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; NOOPT-LABEL: test_comm:
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; NOOPT: # %bb.0: # %entry
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; NOOPT-NEXT: addis 3, 2, comm_glob@toc@ha
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; NOOPT-NEXT: addi 5, 3, comm_glob@toc@l
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; NOOPT-NEXT: lwz 3, 0(5)
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; NOOPT-NEXT: addi 4, 3, 1
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; NOOPT-NEXT: stw 4, 0(5)
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; NOOPT-NEXT: extsw 3, 3
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; NOOPT-NEXT: blr
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;
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; STATIC-LABEL: test_comm:
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; STATIC: # %bb.0: # %entry
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; STATIC-NEXT: addis 4, 2, comm_glob@toc@ha
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; STATIC-NEXT: lwa 3, comm_glob@toc@l(4)
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; STATIC-NEXT: addi 5, 3, 1
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; STATIC-NEXT: stw 5, comm_glob@toc@l(4)
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; STATIC-NEXT: blr
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;
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; PIC-LABEL: test_comm:
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; PIC: # %bb.0: # %entry
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; PIC-NEXT: addis 3, 2, .LC0@toc@ha
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; PIC-NEXT: ld 4, .LC0@toc@l(3)
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; PIC-NEXT: lwa 3, 0(4)
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; PIC-NEXT: addi 5, 3, 1
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; PIC-NEXT: stw 5, 0(4)
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; PIC-NEXT: blr
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entry:
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%0 = load i32, i32* @comm_glob, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @comm_glob, align 4
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ret i32 %0
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}
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