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clang-p2996/llvm/test/CodeGen/RISCV/rvv
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Monk Chiang ee2cb90e3b [RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics. 
We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Monk Chiang <monk.chiang@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93366
2020-12-18 10:24:24 +08:00
..
add-vsetvli-gpr.mir
[RISCV] Refine vector load/store tablegen pattern, NFC.
2020-12-15 18:55:55 -08:00
add-vsetvli-vlmax.ll
[RISCV] Refine vector load/store tablegen pattern, NFC.
2020-12-15 18:55:55 -08:00
cleanup-vsetvli.mir
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-8.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-16.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-32.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-64.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
vadc-rv32.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vadc-rv64.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vadd-rv32.ll
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
2020-12-15 12:56:49 +08:00
vadd-rv64.ll
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
2020-12-15 12:56:49 +08:00
vdiv-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vdiv-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vdivu-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vdivu-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vfadd-rv32.ll
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
2020-12-16 06:31:47 +08:00
vfadd-rv64.ll
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
2020-12-16 06:31:47 +08:00
vfrsub-rv32.ll
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
2020-12-16 06:31:47 +08:00
vfrsub-rv64.ll
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
2020-12-16 06:31:47 +08:00
vfsub-rv32.ll
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
2020-12-16 06:31:47 +08:00
vfsub-rv64.ll
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
2020-12-16 06:31:47 +08:00
vle-rv32.ll
[RISCV] V does not imply F.
2020-12-17 10:57:36 +08:00
vle-rv64.ll
[RISCV] V does not imply F.
2020-12-17 10:57:36 +08:00
vlse-rv32.ll
[RISCV] Define vlse/vsse intrinsics.
2020-12-17 17:00:01 -08:00
vlse-rv64.ll
[RISCV] Define vlse/vsse intrinsics.
2020-12-17 17:00:01 -08:00
vmadc-rv32.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmadc-rv64.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmadc.carry.in-rv32.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmadc.carry.in-rv64.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmax-rv32.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vmax-rv64.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vmaxu-rv32.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vmaxu-rv64.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vmin-rv32.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vmin-rv64.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vminu-rv32.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vminu-rv64.ll
[RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
2020-12-16 06:31:47 +08:00
vmsbc-rv32.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmsbc-rv64.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmsbc.borrow.in-rv32.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmsbc.borrow.in-rv64.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vmul-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmul-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmulh-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmulh-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmulhsu-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmulhsu-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmulhu-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vmulhu-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vnsra-rv32.ll
[RISCV] Define vnsrl/vnsra intrinsics.
2020-12-16 06:31:47 +08:00
vnsra-rv64.ll
[RISCV] Define vnsrl/vnsra intrinsics.
2020-12-16 06:31:47 +08:00
vnsrl-rv32.ll
[RISCV] Define vnsrl/vnsra intrinsics.
2020-12-16 06:31:47 +08:00
vnsrl-rv64.ll
[RISCV] Define vnsrl/vnsra intrinsics.
2020-12-16 06:31:47 +08:00
vrem-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vrem-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vremu-rv32.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vremu-rv64.ll
[RISCV] Define vector mul/div/rem intrinsics.
2020-12-17 11:50:17 +08:00
vrsub-rv32.ll
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
2020-12-15 12:56:49 +08:00
vrsub-rv64.ll
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
2020-12-15 12:56:49 +08:00
vsadd-rv32.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vsadd-rv64.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vsaddu-rv32.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vsaddu-rv64.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vsbc-rv32.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vsbc-rv64.ll
[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
2020-12-16 06:31:47 +08:00
vse-rv32.ll
[RISCV] V does not imply F.
2020-12-17 10:57:36 +08:00
vse-rv64.ll
[RISCV] V does not imply F.
2020-12-17 10:57:36 +08:00
vsll-rv32.ll
[RISCV] Define vsll/vsrl/vsra intrinsics.
2020-12-16 06:31:47 +08:00
vsll-rv64.ll
[RISCV] Define vsll/vsrl/vsra intrinsics.
2020-12-16 06:31:47 +08:00
vsra-rv32.ll
[RISCV] Define vsll/vsrl/vsra intrinsics.
2020-12-16 06:31:47 +08:00
vsra-rv64.ll
[RISCV] Define vsll/vsrl/vsra intrinsics.
2020-12-16 06:31:47 +08:00
vsrl-rv32.ll
[RISCV] Define vsll/vsrl/vsra intrinsics.
2020-12-16 06:31:47 +08:00
vsrl-rv64.ll
[RISCV] Define vsll/vsrl/vsra intrinsics.
2020-12-16 06:31:47 +08:00
vsse-rv32.ll
[RISCV] Define vlse/vsse intrinsics.
2020-12-17 17:00:01 -08:00
vsse-rv64.ll
[RISCV] Define vlse/vsse intrinsics.
2020-12-17 17:00:01 -08:00
vssub-rv32.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vssub-rv64.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vssubu-rv32.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vssubu-rv64.ll
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
2020-12-18 10:24:24 +08:00
vsub-rv32.ll
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
2020-12-15 12:56:49 +08:00
vsub-rv64.ll
[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.
2020-12-15 12:56:49 +08:00
vwadd-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwadd-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwadd.w-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwadd.w-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwaddu-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwaddu-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwaddu.w-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwaddu.w-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwmul-rv32.ll
[RISCV] Define vector widening mul intrinsics.
2020-12-17 11:50:33 +08:00
vwmul-rv64.ll
[RISCV] Define vector widening mul intrinsics.
2020-12-17 11:50:33 +08:00
vwmulsu-rv32.ll
[RISCV] Define vector widening mul intrinsics.
2020-12-17 11:50:33 +08:00
vwmulsu-rv64.ll
[RISCV] Define vector widening mul intrinsics.
2020-12-17 11:50:33 +08:00
vwmulu-rv32.ll
[RISCV] Define vector widening mul intrinsics.
2020-12-17 11:50:33 +08:00
vwmulu-rv64.ll
[RISCV] Define vector widening mul intrinsics.
2020-12-17 11:50:33 +08:00
vwsub-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsub-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsub.w-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsub.w-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsubu-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsubu-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsubu.w-rv32.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00
vwsubu.w-rv64.ll
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
2020-12-15 20:15:06 +08:00