969e703427
Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
186 lines
5.3 KiB
LLVM
186 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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;; This tests how good we are at materialising constants using `select`. The aim
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;; is that we do so without a branch if possible (at the moment our lowering of
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;; select always introduces a branch).
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;;
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;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
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;; constants are either 1 away from each other, or one is a power of two and
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;; the other is zero.
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define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
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; RV32I-LABEL: select_const_int_easy:
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; RV32I: # %bb.0:
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: select_const_int_easy:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: select_const_int_easy:
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; RV64I: # %bb.0:
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: select_const_int_easy:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: ret
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%1 = select i1 %a, i32 1, i32 0
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ret i32 %1
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}
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define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
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; RV32I-LABEL: select_const_int_one_away:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a1, zero, 4
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: select_const_int_one_away:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi a1, zero, 4
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; RV32IF-NEXT: sub a0, a1, a0
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: select_const_int_one_away:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a1, zero, 4
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: select_const_int_one_away:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi a1, zero, 4
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; RV64IFD-NEXT: sub a0, a1, a0
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; RV64IFD-NEXT: ret
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%1 = select i1 %a, i32 3, i32 4
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ret i32 %1
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}
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define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
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; RV32I-LABEL: select_const_int_pow2_zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 2
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: select_const_int_pow2_zero:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: slli a0, a0, 2
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: select_const_int_pow2_zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: select_const_int_pow2_zero:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: slli a0, a0, 2
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; RV64IFD-NEXT: ret
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%1 = select i1 %a, i32 4, i32 0
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ret i32 %1
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}
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define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
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; RV32I-LABEL: select_const_int_harder:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: addi a0, zero, 6
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; RV32I-NEXT: bnez a1, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: addi a0, zero, 38
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: select_const_int_harder:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: mv a1, a0
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; RV32IF-NEXT: addi a0, zero, 6
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; RV32IF-NEXT: bnez a1, .LBB3_2
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; RV32IF-NEXT: # %bb.1:
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; RV32IF-NEXT: addi a0, zero, 38
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; RV32IF-NEXT: .LBB3_2:
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: select_const_int_harder:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a1, a0
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; RV64I-NEXT: addi a0, zero, 6
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; RV64I-NEXT: bnez a1, .LBB3_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: addi a0, zero, 38
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; RV64I-NEXT: .LBB3_2:
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: select_const_int_harder:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: mv a1, a0
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; RV64IFD-NEXT: addi a0, zero, 6
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; RV64IFD-NEXT: bnez a1, .LBB3_2
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; RV64IFD-NEXT: # %bb.1:
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; RV64IFD-NEXT: addi a0, zero, 38
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; RV64IFD-NEXT: .LBB3_2:
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; RV64IFD-NEXT: ret
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%1 = select i1 %a, i32 6, i32 38
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ret i32 %1
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}
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define float @select_const_fp(i1 zeroext %a) nounwind {
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; RV32I-LABEL: select_const_fp:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: lui a0, 263168
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; RV32I-NEXT: bnez a1, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: lui a0, 264192
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: select_const_fp:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: bnez a0, .LBB4_2
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; RV32IF-NEXT: # %bb.1:
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; RV32IF-NEXT: lui a0, %hi(.LCPI4_0)
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; RV32IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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; RV32IF-NEXT: .LBB4_2:
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; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)
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; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: select_const_fp:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a1, a0
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; RV64I-NEXT: lui a0, 263168
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; RV64I-NEXT: bnez a1, .LBB4_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: lui a0, 264192
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: select_const_fp:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: bnez a0, .LBB4_2
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; RV64IFD-NEXT: # %bb.1:
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; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)
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; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
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; RV64IFD-NEXT: fmv.x.w a0, ft0
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; RV64IFD-NEXT: ret
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; RV64IFD-NEXT: .LBB4_2:
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; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)
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; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
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; RV64IFD-NEXT: fmv.x.w a0, ft0
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; RV64IFD-NEXT: ret
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%1 = select i1 %a, float 3.0, float 4.0
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ret float %1
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}
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