Sebastian Neubauer 409a2f0f9e [AMDGPU] Allow no saddr for global addtid insts ...

I think the global_load/store_dword_addtid instructions support
switching off the scalar address.
Add assembler and disassembler support for this.

Differential Revision: https://reviews.llvm.org/D93288

2020-12-16 10:01:40 +01:00

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aperture-regs.ll

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atomic-fadd-insts.txt

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buf_fmt_packed_d16.txt

[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier

2020-07-24 16:41:03 +03:00

buf_fmt_unpacked_d16.txt

[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier

2020-07-24 16:41:03 +03:00

decode-err.txt

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dl-insts.txt

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dpp_gfx9.txt

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dpp_vi.txt

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ds_vi.txt

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exp_gfx10.txt

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exp_vi.txt

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flat_gfx9.txt

AMDGPU: Fix global atomic saddr operand class

2020-08-15 12:12:28 -04:00

flat_gfx10.txt

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flat_vi.txt

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gfx8_dasm_all.txt

[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds

2020-10-29 17:31:59 +00:00

gfx9_dasm_all.txt

[AMDGPU][NFC] Add more global_atomic_cmpswap tests

2020-12-15 14:47:33 +01:00

gfx10_dasm_all.txt

[AMDGPU][NFC] Add more global_atomic_cmpswap tests

2020-12-15 14:47:33 +01:00

gfx10_dasm_dpp8.txt

[AMDGPU] Use lowercase for subtarget feature names in RUN lines

2020-10-13 09:02:09 +01:00

gfx10_dasm_dpp16.txt

[AMDGPU] Use lowercase for subtarget feature names in RUN lines

2020-10-13 09:02:09 +01:00

gfx10_mimg.txt

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gfx10-sgpr-max.txt

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gfx10-vop2be-literal.txt

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gfx1011_dasm_dlops.txt

[AMDGPU] Add gfx1033 target

2020-11-03 16:27:48 +00:00

gfx1030_dasm_new.txt

[AMDGPU] Allow no saddr for global addtid insts

2020-12-16 10:01:40 +01:00

lds_direct_gfx9.txt

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lit.local.cfg

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literal16_vi.txt

[AMDGPU][MC] Corrected decoding of 16-bit literals

2020-07-22 17:20:43 +03:00

literal_gfx9.txt

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literal_vi.txt

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literalv216_gfx10.txt

AMDGPU: Don't use 16-bit FP inline constants in integer operands

2020-06-17 19:14:10 -04:00

mac.txt

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mad_mix.txt

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mai.txt

[AMDGPU] Set default op_sel_hi on accvgpr read/write

2020-11-10 13:07:29 -08:00

mimg_vi.txt

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mov.txt

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mtbuf_gfx10.txt

[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier

2020-07-24 16:41:03 +03:00

mtbuf_vi.txt

[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier

2020-07-24 16:41:03 +03:00

mubuf_gfx9.txt

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mubuf_gfx10.txt

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mubuf_vi.txt

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nop.txt

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null-reg.txt

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sdwa_gfx9.txt

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sdwa_vi.txt

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si-support.txt

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smem_gfx9.txt

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smem_vi.txt

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smrd_vi.txt

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sop1_gfx9.txt

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sop1_vi.txt

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sop2_gfx9.txt

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sop2_gfx10.txt

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sop2_vi.txt

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sopc_vi.txt

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sopk_gfx9.txt

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sopk_vi.txt

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sopp_vi.txt

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trap_gfx9.txt

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trap_vi.txt

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vcmp-gfx10.txt

[MC][Disassembler][AMDGPU] Remove unused check prefix

2020-11-10 13:10:12 +00:00

vcmpx-gfx10.txt

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vintrp.txt

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vop1_gfx9.txt

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vop1_vi.txt

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vop1.txt

[AMDGPU][MC] Corrected decoding of 16-bit literals

2020-07-22 17:20:43 +03:00

vop2_vi.txt

[AMDGPU][MC][GFX8+] Enabled clamp for v_add_u16, v_sub_u16 and v_subrev_u16

2020-05-25 19:55:38 +03:00

vop3_gfx9.txt

[AMDGPU] Fix check prefix for VOP3 VI disassembler tests

2020-10-27 18:43:25 +00:00

vop3_vi.txt

[AMDGPU] Fix check prefix for VOP3 VI disassembler tests

2020-10-27 18:43:25 +00:00

vop3-literal.txt

[AMDGPU][MC] Corrected decoding of 16-bit literals

2020-07-22 17:20:43 +03:00

vopc_vi.txt

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wave32.txt

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xdl-insts-gfx908.txt

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xdl-insts-gfx1011-gfx1012.txt

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