9529597cf4
This was reverted because of a miscompilation. At closer inspection, the problem was actually visible in a changed llvm regression test too. This one-line follow up fix/recommit will splat the IV, which is what we are trying to avoid if unnecessary in general, if tail-folding is requested even if all users are scalar instructions after vectorisation. Because with tail-folding, the splat IV will be used by the predicate of the masked loads/stores instructions. The previous version omitted this, which caused the miscompilation. The original commit message was: If tail-folding of the scalar remainder loop is applied, the primary induction variable is splat to a vector and used by the masked load/store vector instructions, thus the IV does not remain scalar. Because we now mark that the IV does not remain scalar for these cases, we don't emit the vector IV if it is not used. Thus, the vectoriser produces less dead code. Thanks to Ayal Zaks for the direction how to fix this.
103 lines
5.6 KiB
LLVM
103 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
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define void @test(float* %A, i32 %x) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
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; CHECK: vector.scevcheck:
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; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[X:%.*]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = or i1 false, [[IDENT_CHECK]]
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; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 undef)
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; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
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; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 0, [[MUL_RESULT]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP1]], 0
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; CHECK-NEXT: [[TMP5:%.*]] = select i1 false, i1 [[TMP3]], i1 [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP5]], [[MUL_OVERFLOW]]
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; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP0]], [[TMP6]]
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; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 undef)
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; CHECK-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
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; CHECK-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
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; CHECK-NEXT: [[TMP8:%.*]] = add i32 1, [[MUL_RESULT2]]
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; CHECK-NEXT: [[TMP9:%.*]] = sub i32 1, [[MUL_RESULT2]]
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; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i32 [[TMP9]], 1
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; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP8]], 1
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; CHECK-NEXT: [[TMP12:%.*]] = select i1 false, i1 [[TMP10]], i1 [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW3]]
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; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]
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; CHECK-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[TMP15]], 1
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; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
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; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[X]]
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; CHECK-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
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; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[TMP19]]
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; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 0
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; CHECK-NEXT: [[TMP22:%.*]] = bitcast float* [[TMP21]] to <4 x float>*
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, <4 x float>* [[TMP22]], align 4
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; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[INDEX]] to i32
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; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP23]], 0
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; CHECK-NEXT: [[TMP25:%.*]] = mul i32 [[TMP24]], [[X]]
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; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP25]] to i64
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; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[TMP26]]
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; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds float, float* [[TMP27]], i32 0
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; CHECK-NEXT: [[TMP29:%.*]] = bitcast float* [[TMP28]] to <4 x float>*
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; CHECK-NEXT: store <4 x float> [[WIDE_LOAD]], <4 x float>* [[TMP29]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef
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; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 undef, undef
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ undef, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[T_IV_NEXT:%.*]] = trunc i64 [[IV_NEXT]] to i32
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; CHECK-NEXT: [[MUL_IV_NEXT:%.*]] = mul i32 [[T_IV_NEXT]], [[X]]
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; CHECK-NEXT: [[IDX_1:%.*]] = zext i32 [[MUL_IV_NEXT]] to i64
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; CHECK-NEXT: [[ARRAYIDX1215:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[IDX_1]]
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; CHECK-NEXT: [[LV:%.*]] = load float, float* [[ARRAYIDX1215]], align 4
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; CHECK-NEXT: [[T_IV:%.*]] = trunc i64 [[IV]] to i32
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; CHECK-NEXT: [[MUL_IV:%.*]] = mul i32 [[T_IV]], [[X]]
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; CHECK-NEXT: [[IDX_2:%.*]] = zext i32 [[MUL_IV]] to i64
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; CHECK-NEXT: [[ARRAYIDX1209:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[IDX_2]]
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; CHECK-NEXT: store float [[LV]], float* [[ARRAYIDX1209]], align 4
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], undef
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; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop !2
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]
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%iv.next = add nuw nsw i64 %iv, 1
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%t.iv.next = trunc i64 %iv.next to i32
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%mul.iv.next = mul i32 %t.iv.next, %x
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%idx.1 = zext i32 %mul.iv.next to i64
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%arrayidx1215 = getelementptr inbounds float, float* %A, i64 %idx.1
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%lv = load float, float* %arrayidx1215, align 4
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%t.iv = trunc i64 %iv to i32
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%mul.iv = mul i32 %t.iv, %x
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%idx.2 = zext i32 %mul.iv to i64
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%arrayidx1209 = getelementptr inbounds float, float* %A, i64 %idx.2
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store float %lv, float* %arrayidx1209, align 4
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%ec = icmp eq i64 %iv.next, undef
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br i1 %ec, label %exit, label %loop
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exit: ; preds = %loop
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ret void
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}
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